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1. 发明专利

JP2003046806A Image signal recorder and image signal processor 审中-公开
标题翻译：图像信号记录器和图像信号处理器
公开(公告)号：JP2003046806A
公开(公告)日：2003-02-14
申请号：JP2001232304
申请日：2001-07-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TABATA AKIFUMI , WATANABE KATSUYUKI , NONAKA TOMOYUKI , MORO EIJI , HORI HIROYUKI
IPC分类号： H04N5/08 , H04N5/91
摘要： PROBLEM TO BE SOLVED: To reliably separate a synchronous signal from an image signal even if an amplitude of the synchronous signal of the image signal fluctuates.
SOLUTION: A minimum level detection circuit 32 detects a minimum level value (b) at a synchronous top end level of an image signal (a) from an LPF 31, and further a pedestal level detection circuit 33 detects a pedestal level value (c) of an image signal (a). A synchronous signal amplitude detection circuit 34 detects an amplitude value (d) of a synchronous signal of the image signal (a) from the detected minimum level value (b) and pedestal level value (c). A coefficient unit 35 multiplies this amplitude value (d) by a coefficient K (0
摘要翻译：要解决的问题：即使图像信号的同步信号的振幅波动，也可以将图像信号的同步信号可靠地分离。解决方案：最小电平检测电路32从LPF31检测图像信号（a）的同步顶端电平的最小电平值（b），并且基准电平检测电路33进一步检测基座电平值（c）的图像信号（a）。同步信号振幅检测电路34根据检测出的最小电平值（b）和基准电平值（c）检测图像信号（a）的同步信号的振幅值（d）。系数单元35将该振幅值（d）乘以系数K（0

2. 发明专利

JPH11275601A Chroma signal processor 失效
标题翻译：色谱信号处理器
公开(公告)号：JPH11275601A
公开(公告)日：1999-10-08
申请号：JP7949598
申请日：1998-03-26
申请人： Hitachi Ltd , Hitachi Video & Inf Syst Inc , 株式会社日立画像情報システム , 株式会社日立製作所
发明人： MORO EIJI , WATANABE KATSUYUKI , TABATA AKIFUMI , KASHIYA HIDEO
IPC分类号： H04N9/83 , H04N9/68 , H04N9/793
摘要： PROBLEM TO BE SOLVED: To eliminate an analog ACC amplifier and an analog ACC detection part and to reduce the cost of a chroma signal processor by preparing an ACC gain control part, consisting of an ACC amplifier and an ACC detection part at only a digital signal processing part.
SOLUTION: A digital ACC circuit part, consisting of an ACC amplifier 40 and an ACC detection part 41, is prepared at a digital signal processing part 47. The amplifier 40 is placed at the preceding stage of a decoder 5 and controlled by the output received from the part 41. Since the configuration is such that the ACC detection input signal of the part 41 is given from a position set after a switch 7, the disturbance of adjacent crosstalks can accordingly be avoided. The position where the amplifier 40 is inserted is set at a position right after an A/D converter 4, i.e., at the preceding stage of the decoder 5. Thereby, the amplitudes of signals which are processed by the circuits of the subsequent stages including the decoder 5, a comb filter 6, etc., are all stabilized, and the problems including the overflow, etc., will hardly occur.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：为了消除模拟ACC放大器和模拟ACC检测部件，并且通过准备ACC增益控制部分来降低色度信号处理器的成本，该增益控制部分由只有数字信号的ACC放大器和ACC检测部分组成处理部分。解决方案：在数字信号处理部分47处准备由ACC放大器40和ACC检测部分41组成的数字ACC电路部分。放大器40被放置在解码器5的前一级并被接收的输出控制由于部件41的ACC检测输入信号是从开关7之后设定的位置给出的，因此可以避免相邻串扰的干扰。将放大器40插入的位置设置在A / D转换器4的正后方的位置，即在解码器5的前一级。由此，由后续级的电路处理的信号的幅度包括解码器5，梳状滤波器6等都是稳定的，并且几乎不会发生包括溢出等的问题。

3. 发明专利

JP2006050660A Video signal processing device 审中-公开
标题翻译：视讯信号处理装置
公开(公告)号：JP2006050660A
公开(公告)日：2006-02-16
申请号：JP2005263162
申请日：2005-09-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MORO EIJI , SODEYAMA TAKESHI , HORI HIROYUKI , WATANABE KATSUYUKI , TABATA AKIFUMI
IPC分类号： H04N5/956 , H04N5/76 , H04N5/92
摘要： PROBLEM TO BE SOLVED: To solve defects such as freeze of an image and block noise when a non-standard signal is inputted to an image compression circuit in a MPEG encoder, etc.
SOLUTION: A time base correction circuit 15 stores an input signal to a memory 6 and reads the stored signal in timing delayed for a predetermined time from V synchronization of the input signal. The circuit 15 resets a reading synchronization generating circuit 9 at each input field. The reset location proceeds 3H or 10H from V synchronization for reading. The circuit 15 detects if the input signal is a non-interlaced signal and field length deviates from a standard value and then corrects odd or even order of a synchronization signal and timing of synchronization. If the input signal is a non-standard signal, the circuit 15 provides a switch 18 which can output without passing image compression circuits 16, 17.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：当在MPEG编码器中的图像压缩电路输入非标准信号时，解决图像冻结和块噪声等缺陷。解决方案：时基校正电路 15将输入信号存储到存储器6，并且从输入信号的V同步延迟预定时间的定时读取存储的信号。电路15在每个输入场复位读取同步发生电路9。复位位置从V同步进行3H或10H读取。电路15检测输入信号是否为非隔行扫描信号，场长度偏离标准值，然后校正同步信号的奇数或偶数阶数和同步定时。如果输入信号是非标准信号，则电路15提供开关18，该开关18可以不经过图像压缩电路16,17输出。（C）2006年，JPO和NCIPI

4. 发明专利

JPH11275390A Video signal reproducing device 失效
标题翻译：视频信号再现设备
公开(公告)号：JPH11275390A
公开(公告)日：1999-10-08
申请号：JP7733298
申请日：1998-03-25
申请人： Hitachi Ltd , Hitachi Video & Inf Syst Inc , 株式会社日立画像情報システム , 株式会社日立製作所
发明人： HORI KAZUAKI , TABATA AKIFUMI , WATANABE KATSUYUKI , TAKAHASHI TOSHIHIDE
IPC分类号： H04N5/21 , H04N5/208
摘要： PROBLEM TO BE SOLVED: To realize video signal reproducing device by which noise is removed by means of a wide frequency band with little signal deterioration, the number of elements is not increased and the deterioration of a characteristic owing to the nonuniformity of the elements and temp. change is eliminated by constituting a noise removing circuit having a contour correcting function by means of a digital signal processing circuit.
SOLUTION: The video signal processing circuit is constituted by a digital circuit and the noise removing circuit is constituted of plural band pass filters using plural delay circuits 202-205 with flat group delay and limitters 214 and 217 permitting outputs to be zero when an input level is large to some extent. A contour signal where a noise component is removed by a slicer 2 by commonly using the plural delay circuits 202-204 used in the noise removing circuit is extracted and added to an original signal so that a contour emphasizing function is provided. The delay circuits are shared by the noise removing circuit and the contour emphasizing circuit, the number of elements is reduced and a signal is processed by the digital circuit so that characteristic deterioration owing to the nonuniformity of the elements and temp. is eliminated.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：为了实现通过具有很小的信号劣化的宽频带去除噪声的视频信号再现装置，元件的数量不会增加，并且由于元件的不均匀性和温度的特性的劣化。通过构成具有通过数字信号处理电路的轮廓校正功能的噪声去除电路来消除变化。解决方案：视频信号处理电路由数字电路构成，噪声去除电路由多个具有平坦组延迟的延迟电路202-205和限制器214和217的带通滤波器构成，允许输出为0，当输入电平在一定程度上是很大的。提取通过共同使用在噪声去除电路中使用的多个延迟电路202-204由限幅器2除去噪声分量的轮廓信号，并将其相加到原始信号，从而提供轮廓强调功能。延迟电路由噪声消除电路和轮廓强调电路共享，元件数量减少，数字电路处理信号，由于元件的不均匀性和温度特性劣化。被淘汰。

5. 发明专利

JPH11234538A DIGITAL CLAMP CIRCUIT 失效
公开(公告)号：JPH11234538A
公开(公告)日：1999-08-27
申请号：JP3699398
申请日：1998-02-19
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： TSUKIJI NOBUYOSHI , ONO KOICHI , WATANABE KATSUYUKI , TABATA AKIFUMI , MORO EIJI
IPC分类号： H04N5/18
摘要： PROBLEM TO BE SOLVED: To obtain the circuit whose signal level is corrected into a desired signal level at all times regardless of occurrence of a noise by obtaining a difference between a received video signal level and a prescribed level, obtaining an averaged level difference that results from dividing the former difference by number of clock cycles for the summing period, applying integration processing to the level difference and adding a level difference obtained by the integration processing to the received video signal. SOLUTION: An integration circuit applies integration processing to a level difference detected by a level difference detection circuit 2 for each 1H. An output of an integration circuit 3 is given to a level difference holding circuit 4 so long as a high level signal from a noise detection signal input terminal is not received. In the case that a high level signal denoting a large level noise or a dropout is received from the noise detection section input terminal 8, no new level difference data are given to the level difference holding circuit 4, and preceding level difference data are left stored in the level difference holding circuit 4. The level difference holding circuit 4 outputs a video signal whose level is corrected to an after correction video signal output terminal 11.

6. 发明专利

JPH10285612A VIDEO SIGNAL PROCESSOR 失效
公开(公告)号：JPH10285612A
公开(公告)日：1998-10-23
申请号：JP13405096
申请日：1996-05-29
申请人： HITACHI LTD , VICTOR COMPANY OF JAPAN
发明人： NONAKA TOMOYUKI , TABATA AKIFUMI , HORI HIROYUKI , OKASAKA AKIRA , SASAKI MASAHIRO , ITO KAZUKI
IPC分类号： H04N9/83 , H04N9/64 , H04N9/68
摘要： PROBLEM TO BE SOLVED: To provide a highly accurate video signal processor at a low cost by integrating an exterior block filter. SOLUTION: This processor is provided with a phase detector 15, a secondary LPF 14 arranged so as to turn the phase difference of the two input signals of the phase detector 15 to 90 degrees, a switching circuit 26 for switching chrominance signals and reference signals in the input of an equalizer 11 and a reference signal elimination circuit 27 for eliminating the reference signals from the chrominance signals in the output of a second equalizer 12. The phase detector 15 and the reference signal elimination circuit 27 are operated in synchronism with the time when the reference signals have been selected and the equalizers 11, 12 and 13 and the secondary LPF 14 are feedback controlled by using the output signals of the phase detector 15.

7. 发明专利

JPH08180583A REPRODUCTION CIRCUIT FOR MAGNETIC RECORDER/REPRODUCER 失效
公开(公告)号：JPH08180583A
公开(公告)日：1996-07-12
申请号：JP32671994
申请日：1994-12-28
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： HIROSE KOICHI , NUNOMURA KUNIHIRO , UEKI YUKIYA , WATANABE KATSUYUKI , TABATA AKIFUMI
IPC分类号： G11B20/06
摘要： PURPOSE: To enhance the S/N ratio while preventing reversal by controlling the frequency characteristics of a reproduction equalizer depending on the output from a reversal detection circuit. CONSTITUTION: A reversal detection circuit 12 detects decrease of amplitude in the envelope of a reproduced FM signal corresponding to a part of video signal where the luminance level varies steeply. When the circuit 12 detects a reversal, a control circuit 13 outputs a signal for modifying the frequency characteristics of a reproduction equalizer 10 so that the high frequency region is emphasized. Frequency characteristics of the reproduction equalizer 10 are controlled adaptively and optimally depending on the reproduced signal thus preventing reversal while enhancing the S/N ratio. Furthermore, a constant amplitude signal is fed from an AGC circuit 9 to the circuit 12 thus suppressing fluctuation in the reversal detection sensitivity due to fluctuation in the sensitivity of of reproduction heads 2, 3.

8. 发明专利

JPH07236156A SIGNAL PROCESSING CIRCUIT FOR MAGNETIC RECORDING/ REPRODUCING DEVICE 失效
公开(公告)号：JPH07236156A
公开(公告)日：1995-09-05
申请号：JP2769994
申请日：1994-02-25
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： HORI KAZUAKI , TABATA AKIFUMI , AZEYANAGI TOMOMITSU
IPC分类号： H04N9/84 , H04N9/88
摘要： PURPOSE:To execute drop-out compensation, the reproduction of a wide band luminance signal and recording/reproducing signal processing only by one delay circuit in a signal processing circuit for a magnetic recording/reproducing device. CONSTITUTION:The delay circuit 22 is used at the time of recording and reproducing in common and a circuit is provided for separating a recording video signal into a luminance signal and a chrominance signal at the time of recording and a drop-out detecting circuit 5 is provided for detecting the omission of a reproduced video signal to compensate drop-out at the time of reproducing, a line noise canceler circuit reduces a noise and a comb filter for chrominance signal is provided for removing adjacent crosstalk. A band limit circuit 15 attenuates components corresponding to the reproduction chrominance signal band of the reproducing luminance signal to cope with the reproduction of a wide band luminance signal.

9. 发明专利

JPH01191586A NOISE REDUCTION CIRCUIT 失效
公开(公告)号：JPH01191586A
公开(公告)日：1989-08-01
申请号：JP1445388
申请日：1988-01-27
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： KOMATSU KEIICHI , TABATA AKIFUMI
IPC分类号： H04N5/21 , H04N5/93
摘要： PURPOSE:To eliminate waveform distortion at an edge part and to obtain an excellent image by providing a first and a second reduction circuits, a first and a second high-pass filters, a first and second limitor circuits, and a first and a second attenuation circuits and obtaining a signal having round edge by the first reduction circuit and processing the signal by the second high-pass filter and the second limitor. CONSTITUTION:A sub-path is provided which consists of the second high-pass filter(HPF) 7 to take out a regenerated video signal in a high frequency band from an input signal, the second limitor 8 to take out noise components of small amplitude from an output from the second HPF 7, and the second attenuation circuit 9 to attenuate an output signal from the second limitor 8. An input signal to this sub-path is made the same as that to the first attenuation circuit 3, and an output signal form the sub-path is subtracted from that from the first subtraction circuit 3. The second HPF 7 is able to take out high frequency components from a signal not yet subjected to a dynamic deemphasis processing, and a signal whose edge part is not rounded can be taken out. As a result, waveform distortion can be reduced at an edge part, hence an excellent reproduced image can be obtained.

10. 发明专利

JPH01105679A VERTICAL CONTOUR EMPHASIZING CIRCUIT 失效
公开(公告)号：JPH01105679A
公开(公告)日：1989-04-24
申请号：JP26156987
申请日：1987-10-19
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： TABATA AKIFUMI , KOMATSU KEIICHI
IPC分类号： H04N5/208 , H04N5/93
摘要： PURPOSE:To improve the sharpness of an image by obtaining a delay circuit to delay a video signal by one horizontal period and a switching circuit to change-over the input of the delay circuit with a recording and a reproducing. CONSTITUTION:As a recording time, a switch 7 is connected as being shown in the figure and a recording luminance signal SI (figure A: however, a horizontal synchronizing signal is omitted) is supplied to a 1H delay circuit 40 and delayed only by one horizontal period TH. Then, this delayed luminance signal SD (figure B) is supplied to an adder 43. In a subtracter 41, an input luminance signal SI (figure A) is subtracted from the luminance signal SD (figure B), which is 1H-delayed, from the 1H delay circuit 40 and a difference signal SA (figure C) is formed. This difference signal SA is allowed to be a suitable level by a level adjusting circuit 45 and supplied to the adder 43. Then, it is added to the above mentioned luminance signal SD (figure B) to be 1H-delayed. A luminance signal SR (figure D), whose outline part is preshot and emphasized, is outputted from the adder 43 to an output terminal 6.

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