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1. 发明专利

JPH11234538A DIGITAL CLAMP CIRCUIT 失效
公开(公告)号：JPH11234538A
公开(公告)日：1999-08-27
申请号：JP3699398
申请日：1998-02-19
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： TSUKIJI NOBUYOSHI , ONO KOICHI , WATANABE KATSUYUKI , TABATA AKIFUMI , MORO EIJI
IPC分类号： H04N5/18
摘要： PROBLEM TO BE SOLVED: To obtain the circuit whose signal level is corrected into a desired signal level at all times regardless of occurrence of a noise by obtaining a difference between a received video signal level and a prescribed level, obtaining an averaged level difference that results from dividing the former difference by number of clock cycles for the summing period, applying integration processing to the level difference and adding a level difference obtained by the integration processing to the received video signal. SOLUTION: An integration circuit applies integration processing to a level difference detected by a level difference detection circuit 2 for each 1H. An output of an integration circuit 3 is given to a level difference holding circuit 4 so long as a high level signal from a noise detection signal input terminal is not received. In the case that a high level signal denoting a large level noise or a dropout is received from the noise detection section input terminal 8, no new level difference data are given to the level difference holding circuit 4, and preceding level difference data are left stored in the level difference holding circuit 4. The level difference holding circuit 4 outputs a video signal whose level is corrected to an after correction video signal output terminal 11.

2. 发明专利

JPH10336696A PROCESSING METHOD FOR COLOR VIDEO SIGNAL 失效
公开(公告)号：JPH10336696A
公开(公告)日：1998-12-18
申请号：JP13818397
申请日：1997-05-28
申请人： HITACHI LTD
发明人： TSUKIJI NOBUYOSHI , ONO KOICHI , TAKASUGI HAJIME , HORIUCHI SUNAO
IPC分类号： H04N9/804 , H04N9/44 , H04N9/78 , H04N9/808 , H04N9/89
摘要： PROBLEM TO BE SOLVED: To prevent color flicker generation on a monitor at the time of freezing Y/C separated video signals by using a memory in a component processing using the clock of 13.5 MHz, then synthesizing luminance signals and chrominance signals again and outputting them. SOLUTION: Counters 27, 28 and 29 and decoders 30, 31 and 32 decide a field and a line to expand/shorten a field period length and switch and perform the expansion and shortening of the field period length of a prescribed field. An oscillation circuit 9 generates the clocks of 27 MHz and a delay circuit 10 delays the signals of 27 MHz for about 8 ns. A multiplexer 11 switches and outputs the clocks without delay and delayed clocks corresponding to the expansion and shortening of the field period length.

3. 发明专利

JPH06350966A PICTURE SIGNAL RECORDER AND PICTURE SIGNAL REPRODUCING DEVICE 失效
公开(公告)号：JPH06350966A
公开(公告)日：1994-12-22
申请号：JP14065793
申请日：1993-06-11
申请人： HITACHI LTD
发明人： OKU MASUO , TSUBOI YUKITOSHI , TAKAHASHI SUSUMU , FUJII YUKIO , ICHIGE KENJI , TSUKIJI NOBUYOSHI
IPC分类号： H04N5/92 , H04N7/00 , H04N7/015
摘要： PURPOSE:To record and reproduce efficiently a MUSE signal and an NTSC signal whose resolution differs from each other entirely. CONSTITUTION:When an NTSC signal is recorded, the NTSC signal is decoded by a decoder 2 and compressed by a picture compression circuit 3b and fed to an error correction coding circuit 5 and a modulation circuit 6. When a MUSE signal with high resolution is recorded, the MUS signal is subjected to interpolation and band limit processing by a MUSE signal decoder 1 and compressed by a picture compression circuit 3a and fed to the error correction coding circuit 5 and the modulation circuit 6 as a signal with nearly equal data rate to that of the NTSC signal. Since the MUSE signal and the NTSC signal whose resolution is entirely different from each other are made to be signals of nearly equal data rate, most of the recording processing circuit and the reproduction processing circuit is used in common for the MUSE signal and the NTSC signal and the recording band of the recording medium is effectively utilized.

4. 发明专利

JP2001166927A INFORMATION PROCESSOR 失效
公开(公告)号：JP2001166927A
公开(公告)日：2001-06-22
申请号：JP35111399
申请日：1999-12-10
申请人： HITACHI LTD , HITACHI MEDIA ELECTRON KK
发明人： TSUKIJI NOBUYOSHI , ITO SHIGEYUKI , KOMATA TAKASHI , TAKAHASHI HIROSHI , TAKAMI MINORU
IPC分类号： G06K17/00 , G06F9/06
摘要： PROBLEM TO BE SOLVED: To solve the problem that it is inconvenient for a user that a PC/SC application is successively selected from a menu, activated and used at the time of turning on an IC card processor when using the IC card processor, which is predicted so that the PC/SC application functioning as a reader-writer to be linked with a PC and also application software of a balance reader or the like as a single body are mounted thereon in the next generation. SOLUTION: At the time of receiving a signal from a connected device recognizing means 201 for recognizing a connected device, an application software selection control means 202 activates a connected device linkage application software. Then the connected device linkage application software can automatically be activated by detecting that the application software is connected to the outside device, thereby improving the convenience for a user.

5. 发明专利

JPH10200884A VIDEO SYNCHRONIZATION SWITCHING DEVICE AND RECORDING AND REPRODUCING DEVICE USING THE SAME 失效
公开(公告)号：JPH10200884A
公开(公告)日：1998-07-31
申请号：JP239397
申请日：1997-01-09
申请人： HITACHI LTD
发明人： TSUKIJI NOBUYOSHI , YAMASHITA KAZUYA , ONO KOICHI , OKADA YOSHINORI
IPC分类号： H04N5/073 , H04N7/18
摘要： PROBLEM TO BE SOLVED: To obtain a video output of higher picture quality by preventing the video output from being switched in a field when asynchronous multi-input videos as a single video signal which is continuously switched. SOLUTION: Video inputs 1 are selected by video selecting circuits 2 and 3 in two stages, the video selected by the 1st selecting means is supplied to a clock generating circuit 3 and the 2nd selecting means, which selects and supplies two video signals to video synchronizing circuits 5 and 6; and the clock generating circuit 4 generates and supplies a clock having the phase locked to a subcarrier to the video synchronizing circuits 5 and 6, which perform writing to an FIFO by using a clock corresponding to the inputted video signal, so that videos synchronized with a synchronizing signal as a reference of output are switched by a system selecting circuit 8 as a video of one system with a readout control signal from an output timing generating circuit 7 and outputted.

6. 发明专利

JPH08275162A DECODING CIRCUIT FOR COMPRESSED DYNAMIC IMAGE REPRODUCTION CIRCUIT 失效
公开(公告)号：JPH08275162A
公开(公告)日：1996-10-18
申请号：JP7278295
申请日：1995-03-30
申请人： HITACHI LTD
发明人： TSUKIJI NOBUYOSHI , TAKAHASHI SUSUMU
IPC分类号： H04N5/7826 , H03M7/00 , H04N5/782 , H04N5/92 , H04N19/423 , H04N19/426 , H04N19/44 , H04N19/46 , H04N19/60 , H04N19/625 , H04N19/70 , H04N19/91 , H04N7/30
摘要： PURPOSE: To realize depacking for ACL (packed code data in bus 1), ACM (that in bus 2) and ACH (that in bus 3) data only with a buffer memory storing code data by one video segment by accessing a required code for depacking to packed code data received by the compressed dynamic image reproduction device. CONSTITUTION: Code data given to a buffer memory 2 are fed to a parallel shifter 3 based on byte information from a code address storage circuit 12 in the unit of bytes. The barrel shifter 3 shifts the code data not decoded by the code length returned from a decode circuit 4 and the bit information from the code address storage circuit 12 and gives the code data fed from the buffer memory 2 to the decode circuit 4.

7. 发明专利

JPH07222094A RECORDING PATTERN IMAGE FORMING METHOD FOR COMPRESSED DYNAMIC IMAGE DATA AND COMPRESSED DYNAMIC IMAGE RECORDER 失效
公开(公告)号：JPH07222094A
公开(公告)日：1995-08-18
申请号：JP910894
申请日：1994-01-31
申请人： HITACHI LTD
发明人： TAKAHASHI SUSUMU , OKU MASUO , TSUBOI YUKITOSHI , TSUKIJI NOBUYOSHI
IPC分类号： H04N5/783 , G11B20/10 , G11B20/12 , H04N5/7826 , H04N5/919 , H04N5/92 , H04N9/804 , H04N19/00 , H04N19/42 , H04N19/423 , H04N19/503 , H04N19/60 , H04N19/61 , H04N19/65 , H04N19/66 , H04N19/70 , H04N19/85 , H04N19/91 , H04N7/24
摘要： PURPOSE:To arrange a recording area efficiently enabling plural high speed reproduction modes by arranging the recording areas for high speed reproduction data in common in different double speed modes. CONSTITUTION:Recording areas 20-24 for 9-fold speed reproduction data in forward and reverse directions and a recording area 3 for triple speed reproduction data in forward and reverse directions are arranged to a recording track 1. The size of each recording areas 20-24 is equal and same data are recorded in the areas 21, 22 and the areas 23, 24. Part of the recording area 3 is used for the recording area 20. For example, tracking is controlled so that a head 4 of + azimuth and a head 5 of - azimuth opposite to each other by 180 deg. trace tracks along broken lines in figure at 9-multiple speed reproduction in the forward direction, for example. A head output is extracted from the recording areas 20, 22, 23 through the tracing through the arrangement of the areas.

8. 发明专利

JPH07161180A REMOTE CONTROL APPARATUS AND RECORDING APPARATUS 失效
公开(公告)号：JPH07161180A
公开(公告)日：1995-06-23
申请号：JP30656493
申请日：1993-12-07
申请人： HITACHI LTD
发明人： TSUKIJI NOBUYOSHI , OKU MASUO , TSUBOI YUKITOSHI , TAKAHASHI SUSUMU
IPC分类号： G11B27/28 , G11B15/02 , G11B27/34
摘要： PURPOSE:To read data recorded in a memory and show the data at a display on a remote control device by connecting the remote control device with the memory. CONSTITUTION:In order to easily obtain index data indicating contents of video signals recorded to a recording medium included in a recording medium housing or data such as momentary positions on the recording medium and the like, the data are stored in a memory 17 installed in the housing. Accompanying data stored in the IC memory 17 in the cassette 16 are read out by a micro- controller 5 of a remote control device 1 connected to the IC memory 17 via a connector, stored in a data-storing circuit 6 and displayed to a display 10 on the remote control device 1 by a data display circuit 9.

9. 发明专利

JPH07111651A MOVING IMAGE COMPRESSION CODING DEVICE AND COMPRESSION MOVING IMAGE RECORDING DEVICE 失效
公开(公告)号：JPH07111651A
公开(公告)日：1995-04-25
申请号：JP25579393
申请日：1993-10-13
申请人： HITACHI LTD
发明人： TAKAHASHI SUSUMU , OKU MASUO , TSUBOI YUKITOSHI , TSUKIJI NOBUYOSHI
IPC分类号： H04N5/92 , G06T9/00 , H04N19/119 , H04N19/126 , H04N19/146 , H04N19/15 , H04N19/159 , H04N19/174 , H04N19/186 , H04N19/423 , H04N19/46 , H04N19/50 , H04N19/503 , H04N19/51 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/65 , H04N19/70 , H04N19/85 , H04N19/89 , H04N19/91 , H04N7/30 , H04N7/32
摘要： PURPOSE:To make an encoding device which is immune to error and is suitable to a high speed reproduction when a coding is performed to moving picture data by using an inter-frame predictive coding. CONSTITUTION:The DC coefficient and the AC coefficient from a DCT conversion quantization circuit 4 are coded in a DC coefficient coding circuit 5 and an AC coefficient coding circuit 6, respectively, and are classified in slices based on the slice synchronizing signal S from a slice synchronizing signal generation circuit 16. At this time, when the frame from an input terminal 1 is set to an intra-frame by a picture mode setting circuit 17, the period of the slice synchronizing signal S at this time becomes 1/2 to 1/5 times as long as that of the slice synchronizing signal S when an input frame is made a non-intra-frame. Thus, the slice size of the intra-frame becomes 1/2 to 1/5 times as long as that of the slice size of the non-intra-frame and the slice sizes of the intra-frame and the non-intra-frame becomes almost equal after coding.

10. 发明专利

JP2005020782A Video data compressing apparatus, video recording and reproducing apparatus, and compression-encoding method of video data 有权
标题翻译：视频数据压缩设备，视频录像和再现设备以及视频数据的压缩编码方法
公开(公告)号：JP2005020782A
公开(公告)日：2005-01-20
申请号：JP2004255634
申请日：2004-09-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ONO KOICHI , NISHIJIMA HIDEO , KANESAKI TAKAYUKI , HORIUCHI SUNAO , TSUKIJI NOBUYOSHI
IPC分类号： H04N19/50 , H03M7/36 , H04N19/423 , H04N19/503 , H04N19/513 , H04N19/61 , H04N19/625 , H04N19/91 , H04N7/32
摘要： PROBLEM TO BE SOLVED: To efficiently perform data compression using predictive encoding for a plurality of video data. SOLUTION: Mixed video data VSMIr resulting from mixing video data inputted to video input terminals 1-4 in a time division manner are segmented for each of the video input terminals 1-4 and written in corresponding memories 6-9 by a memory control circuit 13 in recording. The mixed video data written in the memories 6-9 are then read out of the memories 6-9 in order for the predetermined number of frames. An MPEG encoding circuit 11 then performs predictive encoding between frames for each of the read frames as many as the predetermined number. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：使用多个视频数据的预测编码有效地执行数据压缩。解决方案：对于每个视频输入端子1-4分割输入到视频输入端子1-4的以时分方式输入的视频数据产生的混合视频数据VSMIr，并通过存储器写入相应的存储器6-9 控制电路13进行记录。写入存储器6-9的混合视频数据然后从存储器6-9中读出以便预定数量的帧。然后，MPEG编码电路11对于每个读取帧执行与预定数量一样多的帧之间的预测编码。版权所有（C）2005，JPO＆NCIPI

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