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1. 发明专利

JP2003068740A Semiconductor integrated-circuit device and its manufacturing method 审中-公开
标题翻译：半导体集成电路设备及其制造方法
公开(公告)号：JP2003068740A
公开(公告)日：2003-03-07
申请号：JP2001261614
申请日：2001-08-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： IMAI TOSHINORI , FUJIWARA TAKESHI , SHIRAISHI TOMOHIRO , ASHIHARA YOJI , YOSHIDA MASAAKI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/485
CPC分类号： H01L24/05 , H01L21/76838 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05558 , H01L2224/05624 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent separation of a bonding pad and a dielectric film on its underside.
SOLUTION: A multiplayer film, whose main composition is W having a mechanical strength larger than a wiring 18B whose main conductive layer is an Al alloy film and a bonding pad BP, is formed in an opening 21B formed in a silicon oxide 19, 20, and a multiplayer film 22B is interposed between the wiring 18B and the bonding pad BP.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了防止焊盘和电介质膜在其下侧分离。解决方案：在形成于氧化硅19,20中的开口21B中形成主要成分为具有大于主导电层为Al合金膜的布线18B和焊盘BP的机械强度的W的多层膜，并且在布线18B和接合焊盘BP之间插入多层膜22B。

2. 发明专利

JP2000077555A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2000077555A
公开(公告)日：2000-03-14
申请号：JP26088398
申请日：1998-08-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SHIRAISHI TOMOHIRO , MATSUNAGA TOSHIHIRO , SUWA MOTOHIRO , KUBOSONO MINORU , NOSE FUJIAKI , TSUTSUMI YASUKI , SHIRAI MASAYUKI , MIWA TAKASHI
IPC分类号： H01L23/12
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To ensure proper through-hole conductors and further reduce the pitch of the conductors.
SOLUTION: A BGA 2 of a BGA.IC 1 is provided with a base 3 as a core 4. A ground conductor 5 is formed on the first major surface of the core 4, and an insulating film 9 is formed on the entire ground conductor 5, a plurality of signal lines 10 being formed on the insulating film 9 into a radial pattern. A bonding pad 11 is formed on the inside ends of the signal lines 10, and a pad 12 for bump is connected electrically with the outside ends of the signal lines 10 through the through-hole conductors 15 formed into narrow through- holes 14. Since the pitch of the signal lines can be reduced by forming the through-holes into narrow shape, the wiring density of the signal lines can be improved. In addition, the diameter of the through-holes is small but their length is large and sufficient areas can be ensured on the inner surface of the through-holes. Therefore, the through-hole conductors can be formed properly, and degradation in the electrical characteristics of the through-hole conductors can be prevented.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：确保适当的通孔导体，进一步降低导体间距。解决方案：BGA.IC1的BGA2具有基体3作为芯4.在芯体4的第一主表面上形成接地导体5，并且在整个接地导体上形成绝缘膜9 如图5所示，多个信号线10在绝缘膜9上形成为径向图案。在信号线10的内侧形成有接合焊盘11，通过形成为窄通孔14的通孔导体15，将信号线10的外侧端部与凸起的焊盘12电连接。由于可以通过将通孔形成为窄的形状来减小信号线的间距，可以提高信号线的配线密度。此外，通孔的直径小，但是它们的长度大，并且在通孔的内表面上可以确保足够的面积。因此，可以适当地形成通孔导体，并且可以防止通孔导体的电特性的劣化。

3. 发明专利

JP2004260051A Semiconductor device manufacturing method, and semiconductor device 审中-公开
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：JP2004260051A
公开(公告)日：2004-09-16
申请号：JP2003050642
申请日：2003-02-27
申请人： Hitachi Ltd , Renesas Eastern Japan Semiconductor Inc , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立製作所
发明人： SHIRAISHI TOMOHIRO , TANAKA TAMOTSU , NAGATA TATSUYA , NAKAMARU TSUTOMU , ARAI HIROSHI
IPC分类号： H01L23/12 , H01L23/34 , H01L23/36
CPC分类号： H01L2224/48091 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method and a semiconductor device having a BGA package configuration with a high heat radiating characteristic.
SOLUTION: The semiconductor device manufacturing method has a process for mounting a semiconductor chip 3 on a wiring board 2 via a die bonding material 4, a process for connecting then electrically the semiconductor chip 3 and the wiring board 2 via bonding wires 5, a process for forming then on the wiring board 2 a sealing resin 6 for covering therewith the semiconductor chip 3 and the bonding wires 5, a process for forming thereafter solder balls 9 on the rear surface of the wiring board 2, and a process for adhering a heat radiating plate 8 to the top surface of the sealing resin 6 via an adhering material 7. In this case, an organic material film 8a having high emissivity is applied to the opposite side surface of the heat radiating plate 8 to its surface side whereon it is adhered to the sealing resin 6.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供具有高散热特性的具有BGA封装结构的半导体器件制造方法和半导体器件。解决方案：半导体器件制造方法具有通过管芯接合材料4将半导体芯片3安装在布线板2上的工艺，通过接合线5将半导体芯片3和布线板2电连接的工艺在该布线基板2上形成用于覆盖半导体芯片3和接合线5的密封树脂6，在该布线基板2的背面形成后述的焊锡球9的工序的工序，通过粘接材料7将热辐射板8粘合到密封树脂6的顶面。在这种情况下，将具有高发射率的有机材料膜8a施加到散热板8的相对侧表面在那里粘附到密封树脂6上。（C）2004，JPO＆NCIPI

4. 发明专利

JPH1084012A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH1084012A
公开(公告)日：1998-03-31
申请号：JP23698296
申请日：1996-09-06
申请人： HITACHI LTD
发明人： HIDA AKIHIRO , TSUTSUMI YASUKI , MATSUNAGA TOSHIHIRO , SHIRAISHI TOMOHIRO , KUBOSONO MINORU , KURODA HIROSHI , SHIRAI MASAYUKI
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To sharply reduce a semiconductor chip size and a package size. SOLUTION: Pads 2a are formed on the side faces in all directions of a semiconductor chip 2, leads 3 are electrically connected to the pads 2a directly by soldering, the chip 2 and a part of the leads 3 are rectangularly sealed by a mold resin package 4, and a semiconductor device 1 is formed. The pads 2a are formed in the thickness larger than the wiring formed on the ordinary wiring region by stacking layers of wirings on the scribe area with which a semiconductor wafer is divided into individual semiconductor chips 2 on the prescribed wiring layer, and the pads 2a are exposed to the side face of the semiconductor chip 2 by dicing in such a manner that the pads 2, provided on the scribe area, are divided into two parts when the semiconductor wafer is diced.

5. 发明专利

JPH09326421A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09326421A
公开(公告)日：1997-12-16
申请号：JP16230596
申请日：1996-06-03
申请人： HITACHI LTD
发明人： TSUTSUMI YASUKI , MATSUNAGA TOSHIHIRO , HIDA AKIHIRO , SHIRAISHI TOMOHIRO , KUBOSONO MINORU , KURODA HIROSHI , SHIRAI MASAYUKI
IPC分类号： H01L21/60 , H01L23/12 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To prevent floating of solder balls upon solder-bump formation. SOLUTION: A solder-ball holding tool 30 is prepared. When solder bumps 16 are formed at respective external terminals 15 of a BGA IC (Ball Grid Array Type Semiconductor Integrated Circuit) 25, respective solder balls 33 of the solder-ball holding tool 30 are aligned with the external terminals 15 and reflow soldering is performed. Since the respective solder balls 33 are held by the solder-ball holding tool 30, floating of the solder balls 33 with respect to the external terminals 15 can be prevented in reflow soldering. Accordingly, as solder bumps are appropriately formed in reflow soldering, when packaging the BGA IC 25 to a packaging substrate, connection terminals are appropriately formed with the solder bumps. This prevents conduction failure and short- circuiting. Since the layout and/or size of a holding member of the solder-ball holding tool 30, and the size of the solder ball, can be changed in accordance with the change of specification of the BGA IC, this method can be applied to various products and newly-developed products.

6. 发明专利

JPH09219573A ELECTRONIC DEVICE 失效
公开(公告)号：JPH09219573A
公开(公告)日：1997-08-19
申请号：JP2377696
申请日：1996-02-09
申请人： HITACHI LTD
发明人： HIDA AKIHIRO , MATSUNAGA TOSHIHIRO , TSUTSUMI YASUKI , SHIRAISHI TOMOHIRO , KUBOSONO MINORU , KURODA HIROSHI , SHIRAI MASAYUKI
IPC分类号： H05K1/14 , H05K3/32 , H05K3/40
摘要： PROBLEM TO BE SOLVED: To increase exchange work efficiency of a semiconductor device and reduce the manufacturing cost of electronic devices by a method wherein conductive rubber capable of pulling into or out of an external lead of the semiconductor device is provided on the face of an electrode pad. SOLUTION: A plurality of electrode pads 2 are disposed on the mount face of a mounting board 1, and a conductive rubber 3 capable of pulling into or out of an external lead 10 of a semiconductor device 20 is provided on each face of the plurality of electrode pads 2. By inserting the external lead 10 of the semiconductor device 20 into the conductive rubber 3, the semiconductor device 20 can readily be mounted on the mount face of a mounted board 1, and further by removing the external lead 10 of the semiconductor device 20 inserted into the conductive rubber 3, the semiconductor device 20 can readily be removed from the mounted board 1. Therefore, when a fail is generated in the semiconductor device 20 after mounted, or when an attempt is made to carry out version up of the system, it is possible to increase the exchange work efficiency of the semiconductor device 20.

7. 发明专利

JP2001110837A SEMICONDUCTOR DEVICE AND MANUFACTURING DEVICE THEREOF 失效
公开(公告)号：JP2001110837A
公开(公告)日：2001-04-20
申请号：JP28672599
申请日：1999-10-07
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： TSUTSUMI YASUKI , MATSUNAGA TOSHIHIRO , SHIRAISHI TOMOHIRO , SHIRAI MASAYUKI , SEKI ISAO , ONO HIROMASA
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To prevent the generation of the wire cross of the short wire of BGA with the long wires of the BGA. SOLUTION: A plurality of inner leads 5 for a signal conductor are radially laid on a wiring board 3 of a BGA.LSI, an inner lead 6 for a power supply is laid in a square frame on the inside of a group of the inner leads 5 for the signal conductor and a chip 15 is bonded to a bonding layer 14 on the bottom of a cavity 13 formed in the board 3. When a short wire 17 is wire-bonded between the inner lead 6 and an electrode pad 16 and long wires 18 are respectively wire-bonded between the inner leads 5 and electrode pads 16, the position of the second bonding part of the wire 17 is shifted from the regular position set on the inner lead 6 in the state corresponding to the quantity of the positional deviation from the regular position of the chip 15 and the wire cross of the short wire 17 with the long wires 18 is prevented from being generated. As the result, the generation of a defect in a short-circuit between the wires 17 and 18 due to the wire cross can be prevented.

8. 发明专利

JPH11176979A PACKAGE BASE, ITS MANUFACTURE, SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11176979A
公开(公告)日：1999-07-02
申请号：JP34264197
申请日：1997-12-12
申请人： HITACHI LTD
发明人： SHIRAISHI TOMOHIRO , SHIRAI MASAYUKI , MATSUNAGA TOSHIHIRO , TSUTSUMI YASUKI , HIDA AKIHIRO , KUBOSONO MINORU , KURODA HIROSHI
IPC分类号： H01L23/12 , H05K1/11 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To reduce external size and to attain high mounting density. SOLUTION: This manufacturing process of the package base includes a process in which a wiring layer 13 is formed on a sidewall of a through-hole 12, an organic insulator 16 is embedded to the through-hole 12 of the package base 1 having a pad 13a connecting electrically to the wiring layer 13 to form the organic insulator 16 in the through-hole 12 and a process in which a solder ball (ball grid array (BGA) ball) 17 is placed on the organic insulator 16 and the pad 13a.

9. 发明专利

JPH1187383A MOLDING METHOD AND MOLDING APPARATUS, AND MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH1187383A
公开(公告)日：1999-03-30
申请号：JP24493597
申请日：1997-09-10
申请人： HITACHI LTD
发明人： HIDA AKIHIRO , MATSUNAGA TOSHIHIRO , TSUTSUMI YASUKI , SHIRAISHI TOMOHIRO , KURODA HIROSHI , KUBOSONO MINORU , SHIRAI MASAYUKI
IPC分类号： B29C33/12 , B29C45/02 , B29C45/14 , B29L31/34 , H01L21/56 , H01L23/12 , H01L23/28
摘要： PROBLEM TO BE SOLVED: To make discrete conveyance of semiconductor devices having single- surface molding type resin seal structure and improve the reliability at the same time by the whole-surface adhesion of a sealing resin. SOLUTION: In a molding apparatus, a plurality of fixed projecting sections 31a are formed to a cavity 31 of a top force 30, when whole-surface molding type sealing is conducted, by charging the package base 13 of single-surface molding type semiconductor device into a cavity 21 of a bottom force 20, while upwardly directing the loading surface of a semiconductor pellet 11 and filling the inside of the cavity 31 of the top force 30 with a sealing-resin from a pot 32 via a runner 33 and a gate 34. The package base 13 is held stably into the cavity 21 of the bottom force 20 under the state of mold clamping during sealing operation, by the fixed projecting section 31a at that time. As a result single- surface molding type whole-surface molding can be carried out without a lead frame.

10. 发明专利

JPH1056034A BONDING DEVICE 失效
公开(公告)号：JPH1056034A
公开(公告)日：1998-02-24
申请号：JP21242496
申请日：1996-08-12
申请人： HITACHI LTD
发明人： TSUTSUMI YASUKI , MATSUNAGA TOSHIHIRO , HIDA AKIHIRO , SHIRAISHI TOMOHIRO , KUBOSONO MINORU , KURODA HIROSHI , SHIRAI MASAYUKI
IPC分类号： H01L21/60 , H01L21/607
摘要： PROBLEM TO BE SOLVED: To speed up the wire bonding operation in the wire bonding of an aluminum wire. SOLUTION: After the tip part of a bonding wire W has been bent by a wire bending mechanism to the direction different from the direction where the bonding pads, provided on a semiconductor chip, are lined up, a wire bonding operation is conducted using a capillary 3. For example, when the bonding pad is provided in lateral direction to the main surface of the semiconductor chip and the bonding wire W is bent in longitudinal direction, the wire bar 6b, with which the bonding wire W is bent, moves to longitudinal direction by a wire bar driving part, a bonding operation is conducted after preventing the contact of the bonding pad, with which the bonding wire W, protruding from the capillary 3, is bent in longitudinal direction and adjacently located, and the top part of the bent bonding wire W.

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