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1. 发明专利

JP2002299515A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002299515A
公开(公告)日：2002-10-11
申请号：JP2001105896
申请日：2001-04-04
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： ONO HIROMASA
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To improve yield by preventing wire shorting. SOLUTION: A multilayer interconnection board 2 is provided with a cavity housing a semiconductor chip 1, bonding wirings in three rows around the cavity, and first and second power source electrodes 2c and 2d which are common wirings provided on both sides with a gap 2b in between with respect to the extending direction in the second-row wiring. Further, there are provided a plurality of wires 3 which connect a pad 1a of the semiconductor chip 1 to the corresponding wiring, a sealing which resin-seals the semiconductor chip 1 and the wire 3, and a plurality of bump electrodes provided to the multilayer interconnection board 2. At the end adjoining the gap 2b at the common wiring of the multilayer interconnection board 2, a wiring correction 2h is provided which protrudes from it in the direction across the extending common wiring to correct a bonding coordinate, so that wire shorting caused by wire crossing is prevented.

2. 发明专利

JPH05136144A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05136144A
公开(公告)日：1993-06-01
申请号：JP29731991
申请日：1991-11-13
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： ONO HIROMASA , KIKUCHI HIROSHI , SATO TOSHIHIKO
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To prevent the peeling of an interface between a terminal and a bump elec trode, and improve reliability, by constituting a bump electrode of low melting point conducting metal or alloy of low melting point conducting metal and high melting point conducting metal, and forming a high melting point conducting metal film excel lent in wettability with the low melting point conducting metal, on the bump electrode side of a substratum metal layer. CONSTITUTION:On a terminal 8 of a semiconductor pellet 10 and a terminal 12 of a substrate 13, a bump electrode 1 is formed via substratum metal layer 6. In this semiconductor device, the bump electrode 1 is constituted of low melting point conducting metal or alloy of low melting point conducting metal and high melting point conducting metal, and a high melting point conducting metal film 2 excellent in wettability with the low melting point conducting metal is formed on the bump electrode 1 side of the substratum metal layer 6. An intermetallic compound layer of low melting point conducting metal and high melting point conducting metal is formed on the interface between the bump electrode 1 and the substratum metal layer 6. For example, the low melting point metal is constituted of lead, and the substratum metal layer 6 is constituted of a lamination film composed of a gold film 2, a copper film 3, an alloy film 4 of copper and chromium and a chromium film 5.

3. 发明专利

JP2002026239A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002026239A
公开(公告)日：2002-01-25
申请号：JP2000206749
申请日：2000-07-07
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： ONO HIROMASA
IPC分类号： H01L25/18 , H01L21/60 , H01L25/065 , H01L25/07
摘要： PROBLEM TO BE SOLVED: To provide an optimum loop control operation in the wire bonding operation of a laminated semiconductor chip. SOLUTION: In a BGA-type semiconductor device, a semiconductor chip 3 is mounted on a printed-wiring board 2, and a semiconductor chip 4 is laminated on the semiconductor chip 3. An electrode 3a and an electrode 4a are formed respectively in parts near outer circumferential parts of the semiconductor chips 3, 4, and an intermediary electrode 3b is formed inside the electrode 3a. The electrode 3a and a bonding electrode 2b are connected by a bonding wire 6, and the electrode 4a and the intermediary electrode 3b are bonded by a bonding wire 7. A bonding wire 8 connects the intermediary electrodes 3b to the bonding electrode 2a. The electrode 4a and the bonding electrode 2a are divided by the intermediary electrode 3b so as to be connected by the bonding wires 7, 8. As a result, it is possible to optimize the loop control operation of the bonding wires 7, 8.

4. 发明专利

JP2001110837A SEMICONDUCTOR DEVICE AND MANUFACTURING DEVICE THEREOF 失效
公开(公告)号：JP2001110837A
公开(公告)日：2001-04-20
申请号：JP28672599
申请日：1999-10-07
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： TSUTSUMI YASUKI , MATSUNAGA TOSHIHIRO , SHIRAISHI TOMOHIRO , SHIRAI MASAYUKI , SEKI ISAO , ONO HIROMASA
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To prevent the generation of the wire cross of the short wire of BGA with the long wires of the BGA. SOLUTION: A plurality of inner leads 5 for a signal conductor are radially laid on a wiring board 3 of a BGA.LSI, an inner lead 6 for a power supply is laid in a square frame on the inside of a group of the inner leads 5 for the signal conductor and a chip 15 is bonded to a bonding layer 14 on the bottom of a cavity 13 formed in the board 3. When a short wire 17 is wire-bonded between the inner lead 6 and an electrode pad 16 and long wires 18 are respectively wire-bonded between the inner leads 5 and electrode pads 16, the position of the second bonding part of the wire 17 is shifted from the regular position set on the inner lead 6 in the state corresponding to the quantity of the positional deviation from the regular position of the chip 15 and the wire cross of the short wire 17 with the long wires 18 is prevented from being generated. As the result, the generation of a defect in a short-circuit between the wires 17 and 18 due to the wire cross can be prevented.

5. 发明专利

JP2003229443A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003229443A
公开(公告)日：2003-08-15
申请号：JP2002025433
申请日：2002-02-01
申请人： HITACHI LTD , RENESAS NTHN JP SEMICONDUCTOR
发明人： KASAI NORIHIKO , ONO HIROMASA
IPC分类号： H01L21/56 , H01L23/31
摘要： PROBLEM TO BE SOLVED: To improve production efficiency by preventing resin from leaking. SOLUTION: A semiconductor device comprises a substrate 7 including a plurality of connection terminals 7e formed around a concave portion 7b and a plurality of bump lands 7h arranged around the connection terminals; a semiconductor chip 1 disposed in the concave portion 7b; a plurality of wires 4 for connecting a pad 1a of the semiconductor chip 1 and the connection terminals 7e of the substrate 7; a sealing section embedded in the concave portion 7b; and a plurality of ball electrodes provided on the bump lands 7h of the substrate 7. A dummy wiring 7i covered with a solder resist 7f is formed in a region between the plurality of the connection terminals 7e of the substrate 7 and the plurality of the bump lands 7h, whereby a gap between a mold surface 12d of an upper mold 12 and the surface of the substrate 7 upon clamping the molds is buried with the dummy wiring 7i and the solder resist 7f covering the former, so that sealing resin 8 upon injecting the resin can be prevented from leaking, and as a result production efficiency in molding can be improved. COPYRIGHT: (C)2003,JPO

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