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1. 发明专利

JPS5881361A CONTROL SYSTEM OF COMMUNICATION CONTROLLER 失效
公开(公告)号：JPS5881361A
公开(公告)日：1983-05-16
申请号：JP17967981
申请日：1981-11-11
申请人： HITACHI LTD
发明人： SHIMODA SEIJI
IPC分类号： H04L29/04 , G06F13/00 , G06F13/24
摘要： PURPOSE:To suppress an instantaneous load within the range of the processing ability and to connect circuits more than the processing ability averagely, by returning a signal for showing that transmission and reception are possible to an actuated terminal only within the processing ability range that is provided to a communication controller. CONSTITUTION:When a terminal device 4 is to start data transmission, a starting character is sent out, and a communication controller 2 holds all interruption permit levels of all circuits addresses low; if an interruption is caused by starting character reception, whether the number of circuit in actual operation is within a permitted value or not is confirmed and when so an answer character is sent back to allow a counter for the number of actual operation circuits to go up by one. The number of permitted circuits depends upon the number of dynamic steps incorporated by the number of circuits which are capable of operating by the communication controller 2. If the number of circuits is greater than a permitted number during starting, the interruption level is low, so processing with another priority level is performed and then a program interruption is caused to compare the number of permitted circuit with the number of circuits in actual operation, so that when the permitted number is less, no signal is transmitted to the terminal device.

2. 发明专利

JPS543440A COMMUNICATION CONTROL PROCESS SYSTEM 失效
公开(公告)号：JPS543440A
公开(公告)日：1979-01-11
申请号：JP6787377
申请日：1977-06-10
申请人： HITACHI LTD
发明人： SHIMODA SEIJI
IPC分类号： H04L29/06 , G06F13/00 , H04B1/00
摘要： PURPOSE:To enhance the economical properties of the communication control process system by using the terminal-based codes and thus connecting various kinds of terminals to the same circuit.

3. 发明专利

JPS60117356A INTERRUPTION CONTROL SYSTEM OF COMMUNICATION CONTROLLER 失效
公开(公告)号：JPS60117356A
公开(公告)日：1985-06-24
申请号：JP22412383
申请日：1983-11-30
申请人： HITACHI LTD
发明人： SHIMODA SEIJI
IPC分类号： H04L29/02 , G06F13/00 , G06F13/26
摘要： PURPOSE:To give higher priority to the processing of a high-speed line when the program control is fed to a mixture line of both high-speed and low-speed lines, by registering the line number, etc. requiring a mask after analyzing the desired contents of the mask. CONSTITUTION:The PLi and PLj show program levels (i) and (j) respectively, and the level (i) is set higher than the level (j). In case the program control is fed to a line where both high-speed and low-speed lines coexist in the same communication controller, the desired contents of a mask are analyzed for the generation of a mask request. Then a circuit number requiring a mask is registered together with the cue level number of the PLj, and the PLj processing is executed. If a higher PLi is produced during the execution of the PLj processing, the saved circuit number and cue level are compared with the circuit number and cue level which produced new interruption. When no coincidence is obtained from said comparison, the interruption of the higher PLi is made possible even in a mask mode. Thus it is possible to process the high-speed line with priority.

4. 发明专利

JPS5654538A COMMUNICATION CONTROLLER 失效
公开(公告)号：JPS5654538A
公开(公告)日：1981-05-14
申请号：JP12986779
申请日：1979-10-11
申请人： HITACHI LTD
发明人： SHIMODA SEIJI
IPC分类号： H04L29/02 , G06F9/46 , G06F9/48 , G06F13/00 , H04L13/00
摘要： PURPOSE:To reduce the number of dynamic steps of a program with regard to a communication controller, by analysing and deciding an external state that corresponds to an interruption of the same program interruption level by a hardware means. CONSTITUTION:When an interruption of a certain program interruption level is made, interruption analyzing circuit 1 sets status display register 2 according to the result of an analysis of and decision on the current external state. For example, bit 2-1 and bit 2-2 of register 2 represent a normal interruption and various abnormal interruptions and with output signal S showing interruption existence from analyzing circuit 1, the contents of register 2 are supplied to the input gate group of instruction address register 5 via gate group 3. In start address constant generating circuit 4, the start address of a program that corresponds to the external state is set up as a constant and the start address of the corresponding program is set in register 5 via the input gate group, thereby performing the interruption processing.

5. 发明专利

JPS5567265A TEST SYSTEM OF AUTOMATIC CALLING CIRCUIT 失效
公开(公告)号：JPS5567265A
公开(公告)日：1980-05-21
申请号：JP13989778
申请日：1978-11-15
申请人： HITACHI LTD
发明人： OKAMURA KOUSUKE , SHIMODA SEIJI
IPC分类号： H04M11/06 , H04L29/10 , H04L29/14 , H04M3/24 , H04M11/00
摘要： PURPOSE:To make self-testing of an automatic calling circuit possible without addition of a testing circuit by using two sets of automatic calling circuits and a loop cable. CONSTITUTION:Two sets of automatic calling circuits 4 are provided in automatic calling buffer 2, and each circuit 4 is connected to network control unit 3 through interface cable 6 by circuit control part 1 and a control program. For the operation test of circuits 4, cable 6 of one circuit 4(A) is removed, and this circuit and the other circuit 4(B) are connected by loop cable 7. Next, when circuit 9 of control part 1 sends signals to register group 10 of circuit 4(A) through line 12, signals from register group 10 are sent to circuit 4(B) through level conversion circuit 11 and cable 7, and output signals are stored in data register 8 through line 13. Then, coincidence and incoincidence of transmission and receiving information are detected by the control program.

6. 发明专利

JPS59109943A Circuit processing controlling system of communication control device 失效
标题翻译：通信控制装置的电路处理控制系统
公开(公告)号：JPS59109943A
公开(公告)日：1984-06-25
申请号：JP21835682
申请日：1982-12-15
申请人： Hitachi Ltd
发明人： SHIMODA SEIJI
IPC分类号： H04L29/04 , G06F13/00 , G06F13/12 , G06F15/177
CPC分类号： G06F13/122 , G06F15/177
摘要： PURPOSE:To increase the number of circuits which can be connected actually, comparing with the number of circuits which can be processed simultaneously, in case when the circuit efficiency is low, by controlling the circuit processing in the course of management of the number of circuits which are being processed actually. CONSTITUTION:When a communication control device is started, a program control part 5 supervises an interruption between a circuit processing request and a circuit processing request. When the interruption is generated, whether it is a request interruption or an end interruption is decided, and if it is the request interruption, whether the number N of circuits which can be processed simultaneously is > the number (n) of circuits which are being processed or not is decided. If the number of circuits N is > (n), the number of circuits (n) is brought to an increment by ''1'' and the circuit processing is executed. In case when it is decided that the number of circuits N is
摘要翻译：目的：为了增加实际连接的电路数量，与电路效率低的电路相比，可以同时处理的电路数量，通过在电路数量管理过程中控制电路处理实际上正在处理。构成：当通信控制装置启动时，程序控制部分5监视电路处理请求和电路处理请求之间的中断。当产生中断时，是否确定是请求中断还是结束中断，如果是请求中断，则可以同时处理的电路数N是否>正在进行的电路的数量（n）被处理或不被决定。如果电路数N为>（n），则电路数（n）增加“1”，执行电路处理。在确定电路数N为<=（n）的情况下，将其请求登记在队列8中。当一些电路的处理结束并且产生结束中断时，电路数（n ）被增加了“1”，除非电路处理请求存在于队列8中，否则返回到其原始状态。根据这样的结构，电路效率越低，连接电路的数量越多，可以同时处理的电路数量越多。

7. 发明专利

JPS5559538A CONTROL CARRIER TRACE SYSTEM FOR COMMUNICATION CONTROL UNIT 失效
公开(公告)号：JPS5559538A
公开(公告)日：1980-05-06
申请号：JP13266378
申请日：1978-10-30
申请人： HITACHI LTD
发明人： SHIMODA SEIJI
IPC分类号： H04L29/14 , G06F13/00 , H04L13/00
摘要： PURPOSE:To decrease the order execution time and thus to shorten the process time for trace by carrying out the process with installation of address register AR which stores the trace data into the idle memory, the means which renews the AR with every storage, and others. CONSTITUTION:In case the interruption occurs at the communication control unit and the trace is given, the trace data is taken out of the circuit control table or the external register. And the order pattern is analyzed at order code analysis part 10. When the order to store the trace data is judged, the trace data is stored in the address shown by trace register Rn(5-3'). After this, the address is increased and renewed, and this result is compared with trace final AR(5-2') at the comparator to decide the memory is traced up to the last. And when the final of the memory is decided, the contents of the head AR in the idle area of AR(5-1') is transferred to Rn(5-3') to prepare for the next trace. As a result, the program steps for the trace data collection within the communication control unit can be shortened.

8. 发明专利

JPS5211807A TEST METHOD OF TRANSMISSION AND RECEPTION OF COMMUNICATION CONTROL EQU IPMENT 失效
公开(公告)号：JPS5211807A
公开(公告)日：1977-01-29
申请号：JP8731775
申请日：1975-07-18
申请人： HITACHI LTD
发明人： SHIMODA SEIJI , YAMAMOTO SEIICHIROU
IPC分类号： H04B1/74 , G06F13/00 , H04L1/24
摘要： PURPOSE:Utilization of the spare switching signal of two-way communication control unit for the transmission and reception test.

9. 发明专利

JPS62254253A CONTINUOUS RECEPTION SYSTEM FOR DATA WITH INDEFINITE LENGTH 失效
公开(公告)号：JPS62254253A
公开(公告)日：1987-11-06
申请号：JP9671086
申请日：1986-04-28
申请人： HITACHI LTD
发明人： SHIMODA SEIJI
IPC分类号： G06F13/00
摘要： PURPOSE:To transfer the continuous input data to a host device just with a single read command by defining the end of a command when no data is received for a fixed period of time. CONSTITUTION:An I/O instruction, e.g., a read command for reception of data given from a circuit is received by an interface control part 2-1 from a host device. Then an instruction is given to a data receiving part 2-2 for the reception of data. A detecting part 2-3 detects a text end code while receiving data. When the test end code is detected, the synchronization of characters is released and the characters are waited for to set up the next synchronization. Then a timer 2-4 is actuated to monitor the input of data and the end of the command is decided when no input is given for a prescribed time (10sec, etc.). Thus it is possible to decrease the number of data receiving buffers within the host device.

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