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1. 发明专利

JPH035801A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPH035801A
公开(公告)日：1991-01-11
申请号：JP13903789
申请日：1989-06-02
申请人： HITACHI LTD , HITACHI TECHNO ENG
发明人： KUROKAWA NAOHIRO , SAKURAI YASUSUKE
IPC分类号： G05B19/05
摘要： PURPOSE:To exactly execute a simulation action at a fine timing by giving prescribed delay time to the operation result of a central processing part and feeding it back to the central operation processing part as concerned input information to be controlled. CONSTITUTION:An input part 4 removing chattering and the like at every input signal, the central processing part (CPU) 6 executing a processing in accordance with the content of a sequence program, an output part 5 for transmitting the operation result of CPU 6 to an external load 3, user RAM (memory) 7 in which the sequence program is stored, and a delay element (delay circuit) 9 which is connected to CPU 6 and to which prescribed delay time is set are provided. At the time of the simulation action, the operation result of CPU 6 is fed back to CPU 6 as an input signal by giving it prescribed delay time through the delay circuit 9. Thus, simulation including fine delay timing is accurately executed without connecting a real unit to an external part.

2. 发明专利

JPH0232405A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPH0232405A
公开(公告)日：1990-02-02
申请号：JP18190988
申请日：1988-07-22
申请人： HITACHI LTD
发明人： KUROKAWA NAOHIRO
IPC分类号： G05B19/02 , G05B19/05
摘要： PURPOSE:To obtain a PC which can be simply and freely accessed by a general purpose personal computer by storing a means to store a mode flag in a programmable controller PC and a processing means for an access as a program. CONSTITUTION:A PC 100 fetches an external signal into an input part 2 and an output part 5 drives an external load. Under a system program 7, a CPU 4 executes the control, drives a sequence program storing part 3-a, an arithmetic result storing part 3-b and a latch 9 stored by a personal computer 101 beforehand and an interface I/F 8 transmits and receives an external peripheral device and a signal. When the I/F 8 receives a first code from a series of transmission codes, the corresponding flag is stored, and when the flag is set, an I/O number code or a second special code is received and by the second code, the on/off signal or the timer time corresponding to the I/O code is communicated to a peripheral equipment. The flag is reset by the first code. By the constitution, the PC can be freely accessed with the general purpose personal computer.

3. 发明专利

JPS6474602A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS6474602A
公开(公告)日：1989-03-20
申请号：JP22990587
申请日：1987-09-16
申请人： HITACHI LTD
发明人： KUROKAWA NAOHIRO
IPC分类号： G05B19/05 , G05B19/04
摘要： PURPOSE:To perform the quick processing by executing the comparison processing of the counted result of a pulse signal by hardware and taking the execution result into a CPU part through a three-state buffer. CONSTITUTION:A CPU part 3 issues a step-up signal to step up the count value given from a program 13 to a user memory 4. In case of a two-word instruction, the step-up signal is issued again by the CPU part 3 to store the second word in a memory 4 in a latch 19. Stored contents of the latch 19 are transmitted to the B side of a comparator 18. Meanwhile, the pulse signal from an encoder 9 is counted by a counter 12, and its contents are given to the A side of the comparator 18. The comparator compares the input A with the input B and transmits the output signal of the comparison result to three-state buffers 21a, 21b, and 21c. One of buffers 21a, 21b, and 21c is selected by the output of an address decoder 20, and the result of the comparator 18 is read out to the CPU part 3.

4. 发明专利

JPS6373301A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS6373301A
公开(公告)日：1988-04-02
申请号：JP21711286
申请日：1986-09-17
申请人： HITACHI LTD
发明人： KUROKAWA NAOHIRO
IPC分类号： G05B19/02 , G05B19/048 , G05B19/05
摘要： PURPOSE:To facilitate the generation and the debugging of a program, by displaying the content of the program to be transmitted to an arithmetic unit on a display path during transmission, in a mode that the program is generated in another arithmetic unit. CONSTITUTION:By turning ON the power source of a programmable controller (PC)1, a CPU 7 reads the state of a function change-over switch 25 through an input port 27, and judges the mode as the generating mode of a sequence program by another arithmetic unit if it is turned ON, and a data received by a communication element 16 is displayed on a display unit 12. Next, a received data is processed, and a result is transmitted from the element 16, and also, it is displayed on the display unit 12. Thus, it is possible to facilitate the generation and the debugging of a transmission program.

5. 发明专利

JPS62221002A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS62221002A
公开(公告)日：1987-09-29
申请号：JP6403486
申请日：1986-03-24
申请人： HITACHI LTD
发明人： KUROKAWA NAOHIRO , KOJIMA NOBUYUKI
IPC分类号： G05B19/05 , G05B19/042
摘要： PURPOSE:To obtain a programmable controller PCS which can easily cope with the change of a sequence program by securing a system where a CPU performs the control to transfer the sequence program stored in a sequence program memory part or a data RAM to said RAM or memory part in a read or write function mode of a changeover switch. CONSTITUTION:When a sequence program is copied, a memory pack storing the relevant sequence program is attached to a programmable controller main body 1 via a connector 20. When an operator sets a slide switch 14 at a store position, the terminal of a position 1 has a signal '0' and a CPU 2 decides the signal via an input buffer circuit 12. The CPU 2 decides that the store signal is turned on from a fact that a terminal 1 has a signal '0' and then turns on a pilot lamp 15 via a latch circuit 13 to transfer the contents of a user memory 11 to a data RAM 4. When this transfer is over, the lamp 15 is turned off and it is decided whether the signal of the terminal 1 is equal to '0' or '1'. Then it is decided that the store signal is turned off as long as the signal of the terminal 1 is equal to '1'.

6. 发明专利

JPS6232484B2 失效
公开(公告)号：JPS6232484B2
公开(公告)日：1987-07-15
申请号：JP8075681
申请日：1981-05-29
申请人： HITACHI LTD
发明人： KUROKAWA NAOHIRO , ABE RYOICHI , FUJIWARA TATSUO
IPC分类号： G05B19/05 , G05B9/02 , G05B19/048 , G05B19/07

7. 发明专利

JPS6212635B2 失效
公开(公告)号：JPS6212635B2
公开(公告)日：1987-03-19
申请号：JP15800279
申请日：1979-12-07
申请人： HITACHI LTD
发明人： KUROKAWA NAOHIRO , ABE RYOICHI
IPC分类号： H01R13/703 , H01R13/70

8. 发明专利

JPS6243735A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS6243735A
公开(公告)日：1987-02-25
申请号：JP18170985
申请日：1985-08-21
申请人： HITACHI LTD
发明人： KUROKAWA NAOHIRO
IPC分类号： G06F9/30 , G05B19/02 , G05B19/05 , G06F9/44 , G06F9/45
摘要： PURPOSE:To fix instruction word length and increase in arithmetic processing speed by converting a program in intermediate language read out of the 1st storage means into machine words according to a machine word table stored in the 2nd storage means which a CPU performs arithmetic processing, and carrying out the arithmetic processing. CONSTITUTION:Address decoders 9 and 20 are connected to the CPU3 through an address bus 24 respectively and receive an address signal from the CPU3, so that only an output selected among Y0-Y7 and Y10 is 0 and unselected outputs are 1. The output Y4 of the address decoder is connected to one-side input terminals of two-input AND gates 10 and 11 with negative logic. The other input terminal of the AND gate 10 is connected to the least significant digit bit A0 of the address bus 24 through a signal line 28. Further, the least significant digit bit A0 of the address bus is connected to the other input terminal of the AND gate 11 through an inverter gate 12. Consequently, the instruction word length can be fixed, so the quantity of a sequence program is easily grasped, thereby increasing the arithmetic processing speed.

9. 发明专利

JPS61278905A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS61278905A
公开(公告)日：1986-12-09
申请号：JP11875085
申请日：1985-06-03
申请人： HITACHI LTD
发明人： KUROKAWA NAOHIRO
IPC分类号： G05B19/05 , G05B19/02 , G06F1/08
摘要： PURPOSE:To select and output one arbitrary pulse among pulses at various frequencies by transmitting one signal or a synchronizing signal among plural frequency dividing signals outputted from a frequency dividing circuit to an external load and obtaining the output of a high frequency pulse with a stable period. CONSTITUTION:The frequency dividing circuit 11 frequency-divides several times the output signal of a reference pulse generating circuit 10, and outputs it as a timing signal with the prescribed period. Plural frequency dividing signals including high frequency pulses at around 1 kHz are outputted from the frequency dividing circuit 11. As a result, a selecting circuit 12 selects one signal specified by an external contact point 14 among plural frequency dividing signals, and transmits it to an output part 15. After the selected frequency dividing signal is power-amplified in the output part 15, it is transmitted to the external load through a pulse output terminal 16.

10. 发明专利

JPS59168504A Sequence controller 失效
标题翻译：序列控制器
公开(公告)号：JPS59168504A
公开(公告)日：1984-09-22
申请号：JP4214083
申请日：1983-03-16
申请人： Hitachi Ltd
发明人： FUJIWARA TATSUO , ABE RIYOUICHI , KUROKAWA NAOHIRO , UEMURA TAKESHI , SUZUKI YUKIO , SOGA SATORU
IPC分类号： G05B19/05 , G05B9/02 , G05B19/02 , G05B19/042 , G05B19/048
CPC分类号： G05B19/042 , G05B2219/14141
摘要： PURPOSE:To load and unload a sequence controller during supply of power by resetting the CPU of a peripheral device with an OR of reset signals of both a basic unit and the peripheral device for the sequence controller having CPUs in both the peripheral device and the basic unit. CONSTITUTION:A sequence controller consists of a basic unit 1 and a peripheral device 2. A resetting circuit 5 of the unit 1 works when a short break of >=1 cycle arises to an AC power supply while the device 2 is loaded. Then a CPU3 of the unit 1 is reset, and at the same time a CPU4 of the device 2 is also reset by an OR gate 16. If the device 2 is loaded while the power is supplied to the unit 1, the CPU4 is restarted with a prescribed delay time in response to the time constants of a resistance 10 and a capacitor 12 of a resetting circuit of the device 2 although the reset signal of the unit 1 is already fixed. It is also available to give the hysteresis characteristics between the input and the output of the resetting circuit.
摘要翻译：目的：通过在外围设备和基本设备中具有CPU的序列控制器的基本单元和外围设备的复位信号的OR复位外围设备的CPU，通过复位外围设备的CPU来加载和卸载顺序控制器单元。构成：序列控制器由基本单元1和外围设备2组成。当设备2被加载时，单元1的复位电路5工作在交流电源的时间为> = 1周期的短暂中断时。然后，单元1的CPU3被复位，同时装置2的CPU4也由或门16复位。如果在向单元1提供电力的情况下装载设备2，则重新开始CPU4 具有响应于装置2的复位电路的电阻10和电容器12的时间常数的规定的延迟时间，尽管单元1的复位信号已经固定。也可以在复位电路的输入和输出之间给出滞后特性。

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