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1. 发明专利

JPH0778006A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPH0778006A
公开(公告)日：1995-03-20
申请号：JP22365493
申请日：1993-09-08
申请人： HITACHI LTD
发明人： WAZUMI MASAAKI , FUJIWARA TATSUO
IPC分类号： G05B9/02 , G05B19/048 , G05B19/05
摘要： PURPOSE:To prevent external equipment from malfunctioning by setting a momentary stop permissible time according to the momentary stop permissible time of the external equipment. CONSTITUTION:The programmable controller, equipped with an input part 10, an output part 9, and a CPU 6, is provided with an AC input part 1 which inputs a signal whose output waveform becomes high to the clear input of a counter 2 when the voltage waveform of an AC power source is larger than a certain voltage, an oscillation circuit part 5 which oscillates clock pulses, a counter 2 which counts the clock pulses, a register 4 which stores the momentary stop permissible value set by a user program, and a comparator 3 which compares the count (measured) value of the counter 2 with the momentary stop permissible value in the register 4 and initiates an interruption to the CPU 6 when the count value is equal to or larger than the permissible value. When the interruption is inputted, the CPU 6 executes a specific program and the momentary stop permissible value is set by the user according to the external equipment; and a momentary stop time is accurately measured to properly execute a power-failure-time execution program.

2. 发明专利

JPH05297992A 失效
公开(公告)号：JPH05297992A
公开(公告)日：1993-11-12
申请号：JP10088192
申请日：1992-04-21
申请人： HITACHI LTD
发明人： UCHIYAMA RYOICHI , FUJIWARA TATSUO
IPC分类号： G05B9/02 , G05B19/048 , G05B19/05 , G06F1/30
摘要： PURPOSE:To prevent erroneous input from being performed by providing a control circuit for erroneous input prevention connected to an output terminal for detection and an input data holding circuit which holds the input signal of external input equipment by receiving a signal from the control circuit for erroneous input prevention circuit. CONSTITUTION:Input from a power source 4 for AC input is directly inputted to the input part 1 of a programmable controller without interposing a switch IS. The input data holding circuit 8, for example, a flip-flop is connected to respective input side of an AC input circuit 7, which holds input data (f), respectively. The update of such hold data is performed by a pulse (e), and it is generated by the control circuit 9 for erroneous input prevention based on AC input (a). In other words, no pulse (e) is outputted when the power source 4 for AC input is disconnected, and previous input data in the AC input circuit is held with the holding circuit 8. Thereby, it is possible to input the input signal without having delay and of short length when the erroneous input is prevented from being performed, and to perform control with high reliability.

3. 发明专利

JPS6232484B2 失效
公开(公告)号：JPS6232484B2
公开(公告)日：1987-07-15
申请号：JP8075681
申请日：1981-05-29
申请人： HITACHI LTD
发明人： KUROKAWA NAOHIRO , ABE RYOICHI , FUJIWARA TATSUO
IPC分类号： G05B19/05 , G05B9/02 , G05B19/048 , G05B19/07

4. 发明专利

JPS6186807A Input circuit of programmable controller 失效
标题翻译：可编程控制器的输入电路
公开(公告)号：JPS6186807A
公开(公告)日：1986-05-02
申请号：JP20811284
申请日：1984-10-05
申请人： Hitachi Ltd
发明人： FUJIWARA TATSUO , UEDA AKIHISA
IPC分类号： G05B19/05 , G05B19/02
CPC分类号： G05B19/054 , G05B2219/14144
摘要： PURPOSE:To attain the connection of a programmable controller regardless of the polarity of an external input device by connecting optically a photodetecting element to two light emitting diodes which are connected adversely and in parallel to each other. CONSTITUTION:Two input devices 1 and 10 of polarities npn and pnp adverse to each other are connected to two input terminals 31 of the same structure. Under such conditions, the device 1 of the npn polarity is turned on in the positive AC half-wave mode of an internal AC power supply 11. Thus a diode 15 emits light out of both diodes 14 and 15 which are connected adversely and in parallel to each other. This emitted light is sent to a phototransistor at the secondary side. When the device 10 of the pnp polarity is turned on in a negative half-wave mode, a diode 16 emits light out of both diodes 16 and 17 connected in parallel to each other. This emitted light is transmitted to the secondary side. Thus an ON state is maintained at the secondary side even in a half-wave mode where the diode has no emission of light due to the time constant of a capacitor 7.
摘要翻译：目的：通过将受光元件光学连接到彼此不利地并且彼此并联连接的两个发光二极管，来实现可编程控制器的连接，而不管外部输入设备的极性如何。构成：两个彼此不利的极性npn和pnp的输入装置1和10连接到相同结构的两个输入端31。在这种条件下，npn极性的装置1在内部交流电源11的正交流半波模式中导通。因此，二极管15从两个二极管14和15中发射出来，两个二极管14和15被不利地并联连接对彼此。该发射光被发送到次级侧的光电晶体管。当pnp极性的器件10以负半波模式导通时，二极管16从彼此并联连接的二极管16和17发射出光。该发射光被传输到次级侧。因此，即使在二极管由于电容器7的时间常数而没有发光的半波模式中，二次侧也保持导通状态。

5. 发明专利

JPS59168504A Sequence controller 失效
标题翻译：序列控制器
公开(公告)号：JPS59168504A
公开(公告)日：1984-09-22
申请号：JP4214083
申请日：1983-03-16
申请人： Hitachi Ltd
发明人： FUJIWARA TATSUO , ABE RIYOUICHI , KUROKAWA NAOHIRO , UEMURA TAKESHI , SUZUKI YUKIO , SOGA SATORU
IPC分类号： G05B19/05 , G05B9/02 , G05B19/02 , G05B19/042 , G05B19/048
CPC分类号： G05B19/042 , G05B2219/14141
摘要： PURPOSE:To load and unload a sequence controller during supply of power by resetting the CPU of a peripheral device with an OR of reset signals of both a basic unit and the peripheral device for the sequence controller having CPUs in both the peripheral device and the basic unit. CONSTITUTION:A sequence controller consists of a basic unit 1 and a peripheral device 2. A resetting circuit 5 of the unit 1 works when a short break of >=1 cycle arises to an AC power supply while the device 2 is loaded. Then a CPU3 of the unit 1 is reset, and at the same time a CPU4 of the device 2 is also reset by an OR gate 16. If the device 2 is loaded while the power is supplied to the unit 1, the CPU4 is restarted with a prescribed delay time in response to the time constants of a resistance 10 and a capacitor 12 of a resetting circuit of the device 2 although the reset signal of the unit 1 is already fixed. It is also available to give the hysteresis characteristics between the input and the output of the resetting circuit.
摘要翻译：目的：通过在外围设备和基本设备中具有CPU的序列控制器的基本单元和外围设备的复位信号的OR复位外围设备的CPU，通过复位外围设备的CPU来加载和卸载顺序控制器单元。构成：序列控制器由基本单元1和外围设备2组成。当设备2被加载时，单元1的复位电路5工作在交流电源的时间为> = 1周期的短暂中断时。然后，单元1的CPU3被复位，同时装置2的CPU4也由或门16复位。如果在向单元1提供电力的情况下装载设备2，则重新开始CPU4 具有响应于装置2的复位电路的电阻10和电容器12的时间常数的规定的延迟时间，尽管单元1的复位信号已经固定。也可以在复位电路的输入和输出之间给出滞后特性。

6. 发明专利

JPS57196306A SEQUENCE CONTROLLER 失效
公开(公告)号：JPS57196306A
公开(公告)日：1982-12-02
申请号：JP8075681
申请日：1981-05-29
申请人： HITACHI LTD
发明人： KUROKAWA NAOHIRO , ABE RIYOUICHI , FUJIWARA TATSUO
IPC分类号： G05B19/05 , G05B9/02 , G05B19/048 , G05B19/07
摘要： PURPOSE:To realize a sequence controller which has the high resistance to the noise and the high reliability, by connecting an end of a noise suppressing circuit to a common terminal and at the same time connecting the noise suppressing circuit in parallel to each load group by using the common terminal as a relaying point. CONSTITUTION:An end of a noise suppressing circuit 12 is connected to each terminal group 71, and the other end of the circuit 12 is connected to a common terminal 73 which is provided independently of a common terminal 72. A single line of a load power supply 9 and a common line a load group 8 are connected to the terminal 73. thus a load circuit including a contact group 6, the load group 8 and the power supply 9 is formed by using the terminal 73 as a relaying point. At the same time, the circuit 12 includes no power supply 9 and is connected to each group 8. As a result, the surge voltage which is generated from the group 8 when the current of a load circuit is cut off is absorbed by the circuit 12. With this surge voltage, the noise induced to a relay coil approximate to the group 6 can be suppressed down to such a low level that causes no fault to the operation of a control part.

7. 发明专利

JPS55129767A TEST UNIT FOR CIRCUIT BREAKER 失效
公开(公告)号：JPS55129767A
公开(公告)日：1980-10-07
申请号：JP3690779
申请日：1979-03-30
申请人： HITACHI LTD
发明人： FUJIWARA TATSUO , HORISAKI KOUICHI
IPC分类号： G01R31/00 , H02H3/05
摘要： PURPOSE:To enable to perform operation check simply without interrupting the conduction of load line, by limiting the supply of simulated current to the breaker before the operation of the trip coil through the detection of trip signal and making inoperative the trip coil. CONSTITUTION:When the simulated current I is fed to the terminals TA, TB from the simulated current generation circuit 8, the current I is fed to the control circuit 3 via the detection current supply lines 16, 16'. When the circuit 3 is normally operated, the trip signal S is produced from the terminal 3a after the delay time. The thyristors 7 and 10a are triggered with the signal S. Since the trip coil 4 is an inductive load, time is required to finish the operation, most part of current I flows to the branch circuits 9 and 10 before the excitation of the coil 4, the current I and the current i2 flowing to the coil 4 are both reduced into almost no current. Further, this branch current dirves the display section 9 to display the normal operation of the circuit 3.

8. 发明专利

JPH0157310B2 失效
公开(公告)号：JPH0157310B2
公开(公告)日：1989-12-05
申请号：JP3688079
申请日：1979-03-30
申请人： HITACHI LTD
发明人： FUJIWARA TATSUO , HORISAKI KOICHI
IPC分类号： G01R31/00 , G01R31/327 , G01R31/333 , H02H3/05

9. 发明专利

JPS62169204A SEQUENCE CONTROLLER 失效
公开(公告)号：JPS62169204A
公开(公告)日：1987-07-25
申请号：JP1002286
申请日：1986-01-22
申请人： HITACHI LTD
发明人： FUJIWARA TATSUO , ABE RYOICHI , KUROKAWA NAOHIRO
IPC分类号： G05B19/05 , G05B19/02
摘要： PURPOSE:To simplify a program by providing a stepping counter circuit corresponding to each process in case of the process stepping control of a sequence controller and operating this counter when the stepping condition is satisfied. CONSTITUTION:The sequence controller consists of an input part 2 connected to a contact group 1 as an external input signal source, a CPU 3 as a logic decision part, an output part 6, a program part 7, etc. In this case, a stepping counter circuit 8 corresponding to each process is provided as the means which holds a pertinent process in the turn-on state until the stepping condition of the process stepping control is satisfied. When a specific instruction is called from a user RAM 4, the CPU 3 decides which process the counter 8 indicates; and if this process coincides with the process called from the user program, it is checked whether the stepping condition of the external input is turned on or not. As the result, the counter 8 is stepped if it is turned on, but otherwise, no processings are performed.

10. 发明专利

JPS6112284B2 JPS6112284B2 - 失效
公开(公告)号：JPS6112284B2
公开(公告)日：1986-04-07
申请号：JP13760579
申请日：1979-10-26
申请人： Hitachi Ltd
发明人： KUROKAWA NAOHIRO , FUJIWARA TATSUO
IPC分类号： G05B19/05 , G05B19/02

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