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1. 发明专利

JPS5727330A Process control device 失效
标题翻译：过程控制设备
公开(公告)号：JPS5727330A
公开(公告)日：1982-02-13
申请号：JP10127680
申请日：1980-07-25
申请人： Hitachi Ltd
发明人： MATSUZAKI YOSHIE , HORINO HIROSHI , HATA SEIJI
IPC分类号： G06F13/36 , G05B15/02 , G06F13/00 , G06F13/40
CPC分类号： G06F13/4027
摘要： PURPOSE:To perform controlling inexpensively with high reliability with a simple procedure by transmitting and receiving information between a computer bus and a process input and output bus by way of bus decoders and transmission lines, and stopping the operation of the computer during that time. CONSTITUTION:To make output operation, the address and output data of a digital output device 9 are placed onto a computer bus BC from a computer 1, and an input/output signal is made into output mode. The address and data are placed on a process input and output bus BP by a bus decoder 2 via a parallel to series converter 4 and a series to parallel converter 6, and the device 9 outputs required data. To make input operation next, the signal is fed to a stopping device 3 by the decoder 2 to stop the operation of the computer 1, and the address value is converted 4, 6, and is transmitted onto the bus BP. The input data is transmitted to the bus BC by a bus decoder 8 via a parallel to series converter 7 and a series to parallel converter 5; at the same time a release signal is fed from the device 5 to the device 3.
摘要翻译：目的：通过简单的过程，通过总线解码器和传输线在计算机总线和过程输入和输出总线之间发送和接收信息，以高可靠性执行控制，并在此期间停止计算机的运行。构成：为了进行输出操作，将数字输出装置9的地址和输出数据从计算机1放置到计算机总线BC上，并将输入/输出信号作为输出模式。地址和数据由总线解码器2通过并行串行转换器4和串联到并行转换器6放置在过程输入和输出总线BP上，并且器件9输出所需数据。为了进行输入操作，解码器2将该信号馈送到停止装置3以停止计算机1的操作，并将地址值转换为4,6，并将其发送到总线BP上。输入数据由总线解码器8通过并行串行转换器7和串并联转换器5发送到总线BC; 同时将释放信号从设备5馈送到设备3。

2. 发明专利

JPS61269081A IC TEST SYSTEM 失效
公开(公告)号：JPS61269081A
公开(公告)日：1986-11-28
申请号：JP11038585
申请日：1985-05-24
申请人： HITACHI LTD
发明人： YAMAKI YOJI , HORINO HIROSHI
IPC分类号： G01R31/28 , G06F11/26
摘要： PURPOSE:To enable an output for a circuit simulation to be simply and easily applied to a linear IC tester by providing an execution control table common to both a system for performing a circuit simulation and a linear IC test system. CONSTITUTION:A linear IC tester 1 applies a signal to and observe a socket board 2 which is an interface between a linear IC 3 which is an object to be measured and a linear IC tester 1. When an observed value is within an expected value range prepared in advance, the linear IC is a non-defective and when outside the range, a defective. These execution control processes are performed while the execution control program 7 of a microcomputer system 5 are referring to an execution control table 14. Thus, a test system practically utilizing a simulator and flexibly responding to a semiconductor device manufacturing process can be simply and easily realized.

3. 发明专利

JPS5945577A Addressing system of picture memory 失效
标题翻译：图像存储器寻址系统
公开(公告)号：JPS5945577A
公开(公告)日：1984-03-14
申请号：JP15598782
申请日：1982-09-09
申请人： Hitachi Ltd
发明人： HATA SEIJI , MIYAGAWA AKIRA , HORINO HIROSHI
IPC分类号： G06T1/60
摘要： PURPOSE: To improve the speed of a picture processing, by providing an index register, where decrement and increment for address generation of each adjacent picture element are possible, as an address register for a picture memory.
CONSTITUTION: An initial set address value is loaded from a C bus 9C to respective parallel data input terminals P of counters 11W13 by a data load signal RST. An increment/decrement designating signal UDC, either one of enable signals E1, E2, and E3, and a clock signal CLK are given to update a counted value. The value from its output terminal Q is given as an address ADR to a picture memory 1 to read or write optional picture element data from or into the memory 1. Thus, the address of the picture memory 1 to be referred next is calculated in parallel with another operation processing, and the number of a step of a program is reduced to improve the speed of the picture processing.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了提高图像处理的速度，通过提供索引寄存器，其中每个相邻图像元素的地址生成的递减和增量是可能的，作为图像存储器的地址寄存器。构成：初始设定地址值通过数据负载信号RST从C总线9C加载到计数器11-13的各个并行数据输入端P。给出增量/减量指定信号UDC，使能信号E1，E2和E3中的任一个以及时钟信号CLK，以更新计数值。来自其输出端子Q的值作为地址ADR被给予图像存储器1，以从存储器1读入或写入可选择的图像元素数据。因此，下面要提及的图像存储器1的地址被并行计算进行另一个操作处理，并且减少程序的步骤的数量以提高图像处理的速度。

4. 发明专利

JPS6248858B2 失效
公开(公告)号：JPS6248858B2
公开(公告)日：1987-10-15
申请号：JP5124882
申请日：1982-03-31
申请人： HITACHI LTD
发明人： MATSUZAKI YOSHE , HATA SEIJI , HORINO HIROSHI , OGAWA YASUICHIRO
IPC分类号： G06F3/02 , G06F9/06 , G06F9/44

5. 发明专利

JPS58201168A Picture memory constitution system 失效
标题翻译：图像记忆体系
公开(公告)号：JPS58201168A
公开(公告)日：1983-11-22
申请号：JP8399982
申请日：1982-05-20
申请人： Hitachi Ltd
发明人： HATA SEIJI , HORINO HIROSHI , MIYAGAWA AKIRA , OKAMOTO KEIICHI
IPC分类号： G06T3/00 , G06T1/60
CPC分类号： G06T1/60
摘要： PURPOSE:To discriminate processing content according to discrimination only by a processing code, and to speed up the processing of picture element data in accordance with an area, by dividing the picture element data into plural parts, and inserting processing codes corresponding to picture elements to the prescribed parts. CONSTITUTION:Processing codes characteristic to respective picture elements are written in memory units 20-6 and 20-7 (corresponding to bits D6 and D7) by an initializing program. Then, a register 27A is so set that while the writing of respective picture element data to a processing code part CNT is inhibited, the writing to a picture element data part D is permitted; and bits of the respective picture element data are stored successively in memory units 20-0- 20-5 corresponding to the data part DATA from a picture input interface part. A register 27B, on the other hand, is set in an all-bit read state and a control processing part 1 reads the all data bits D0-D7 of the respective picture element data successively to perform picture processing according to the processing codes.
摘要翻译：目的：为了根据区分处理代码区分处理内容，并且通过将图像元素数据分割成多个部分，并且将对应于图像元素的处理代码插入到规定的部分。构成：通过初始化程序将对各个像素特征的处理码写入存储单元20-6和20-7（对应于位D6和D7）。然后，寄存器27A被设定为：当将各个像素数据写入处理代码部分CNT被禁止时，允许对像素数据部分D的写入; 并且各个像素数据的比特顺序地存储在与图像输入接口部分对应的数据部分DATA的存储单元20-0-20-5中。另一方面，寄存器27B被设置为全位读取状态，并且控制处理部分1依次读取各个像素数据的全部数据位D0-D7，以根据处理代码进行图像处理。

6. 发明专利

JPS57204939A PROCESS INPUT AND OUTPUT REMOTE CONNECTING DEVICE 失效
公开(公告)号：JPS57204939A
公开(公告)日：1982-12-15
申请号：JP8956181
申请日：1981-06-12
申请人： HITACHI LTD
发明人： HATA SEIJI , MATSUZAKI YOSHIE , HORINO HIROSHI , OGAWA YASUICHIROU
IPC分类号： G05B15/02 , G06F13/24 , G06F17/40
摘要： PURPOSE:To make input/output processings high-speed and make the response to an interrupt signal quick, by transmitting data of only an address from which data is outputted or an address where the input state is changed between a controller and input/output terminal. CONSTITUTION:The data output from an operating device 12 of a controller 11 is recognized by a remote interface controller 13 and is inputted to a transmission stack 15 and changes contents of a memory device 14. Data inputted to the stack 15 is transmitted to a remote input/output terminal 19 through a data transmission line 29 immediately when a data transmitting device 17 becomes usable. This data is received in a remote terminal controller 20 through a data transmitting device 21 and is set to a holding device 25 and becomes the output to a process. An input data change detecting circuit 22 checks the state of the holding device 25 for all input and detects changes to send the transmission request to the controller 20. The controller 20 transmits input data to the controller 11, and the controller writes data in the memory device 14.

7. 发明专利

JPS603273A SYSTEM FOR SETTING BINARY-CODING THRESHOLD VALUE OF PICTURE 失效
公开(公告)号：JPS603273A
公开(公告)日：1985-01-09
申请号：JP10937483
申请日：1983-06-20
申请人： HITACHI LTD
发明人： SUZUKI KENJI , HATA SEIJI , MIYAGAWA AKIRA , HORINO HIROSHI , MATSUZAKI YOSHIE
IPC分类号： G06T1/00 , H04N1/403 , H04N1/40 , G06K9/38
摘要： PURPOSE:To set the binary-coded threshold value properly in a short time depending on the lighting condition by providing a mark to a fixed position in a visual field in a system binary-coding a multi-value data and conducting the picture processing. CONSTITUTION:An image of component 2 carried on a conveyor 1 is picked up by a TV camera 4 and the signal is outputted to apicture processing section 5. The processing section 5 binary-codes the transmitted multi-value picture signal to attain processing. In the picture processing system of the constitution above, a fixed mark 3 is provided in the visual field F of the camera 4 and the relation between the lightness of mark and the binary-coded threshold value corresponded thereto is stored in a threshold value setting section 7 of the processor 5. Thus, a component picture binary-coding section 8 in the processor 5 converts a picture of the component 2 being an object into a binary picture by means of the proper binary-coded threshold value corresponding to the lightness of the mark 3.

8. 发明专利

JPS57207926A METHOD FOR INPUTTING GRAPHIC INFORMATION INTO COMPUTER 失效
公开(公告)号：JPS57207926A
公开(公告)日：1982-12-20
申请号：JP9228281
申请日：1981-06-17
申请人： HITACHI LTD
发明人： MIYAGAWA AKIRA , HORINO HIROSHI , SAGA TAKAHARU
IPC分类号： H03M11/04 , G06F3/023 , G06F3/16 , G06F17/50 , G06T11/20
摘要： PURPOSE:To sharply reduce the number of inputting works, by fixing an attribute information area to a topology inputted from a drawing and by selectively and indicatively inputting appropriate information into the information area. CONSTITUTION:A design drawing 1 is read by a pattern reader 2 and line patterns drawn on the drawing are inputted into an arithmetic processor as segment data 3, and then, the data are processed. At the same time, the data are displayed in a graphic display 5 and an instruction that character and numeral information must be inputted one information by one information is given to the designer. Character and numeral information 7 inputted into a sound inputting device 6 in compliance with the instruction is coupled with the pattern information 3 and drawn on the drawing and design information 8 is outputted as digital data. Moreover, when the outputted data are inputted into a computer 9, three-dimensional geometric data can be produced from the digital data and the digital data can be converted into data for various application programs.

9. 发明专利

JPH0451841B2 失效
公开(公告)号：JPH0451841B2
公开(公告)日：1992-08-20
申请号：JP2436282
申请日：1982-02-19
申请人： HITACHI LTD
发明人： MATOBA HIDEAKI , HORINO HIROSHI , HATA SEIJI
IPC分类号： B25J13/00 , B25J9/16 , G05B19/18 , G05B19/4093 , G05B19/4155

10. 发明专利

JPH0283473A IC TESTING APPARATUS 失效
公开(公告)号：JPH0283473A
公开(公告)日：1990-03-23
申请号：JP23505088
申请日：1988-09-21
申请人： HITACHI LTD , HITACHI ELECTR ENG
发明人： KAWAGUCHI IKUO , HORINO HIROSHI
IPC分类号： G01R31/28 , G01R31/3183
摘要： PURPOSE:To enhance throughput by providing hardware for compressing the pattern data of a high speed pattern memory on the basis of a required format and directly storing the same in a large capacity data memory. CONSTITUTION:The data of a compression form mentioned in a large capacity data memory 1 is mentioned in a high speed pattern memory 2 by a comparator 12, a register 13 and a selector 14, and developed data is transmitted to a data compression part 4 to be compressed and automatically stored in the large capacity data memory 1. By this constitution, a processing time becomes 1/several ten as compared with a conventional tester and test throughput can be enhanced.

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