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1. 发明专利

JP2004318170A Liquid crystal display 有权
公开(公告)号：JP2004318170A
公开(公告)日：2004-11-11
申请号：JP2004177874
申请日：2004-06-16
申请人： Hitachi Device Eng Co Ltd , Hitachi Displays Ltd , Hitachi Ulsi Systems Co Ltd , 日立デバイスエンジニアリング株式会社 , 株式会社日立ディスプレイズ , 株式会社日立超エル・エス・アイ・システムズ
发明人： GOTO MITSURU , KATAYANAGI HIROSHI , OTE YUKIHIDE , SAITO YOSHIYUKI , KODERA KOICHI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To secure a timing margin when display data are latched in a semiconductor integrated circuit constituting a video signal line driving means even when a clock for display data latch and the operating frequency of display data are made fast. SOLUTION: A video signal line driving means has a prelatch part which latches display data of one pixel consisting of red, green, and blue by two pixels, bus lines of two systems to which display data of two pixels are transmitted, and a display data switching means of switching and outputting display data of one pixel outputted from the prelatch part to one of the bus lines of the two systems and display data of the other pixel outputted from the prelatch part to the other bus line. Further, provided are a video signal voltage generating means comprising a positive video signal voltage generating means of inputting display data of one of the two systems of bus lines and generates a positive-polarity video signal voltage and a negative video signal voltage generating means of inputting video data of the other bus line, and generates a negative video signal voltage. COPYRIGHT: (C)2005,JPO&NCIPI

2. 发明专利

JP2011112711A Display device 审中-公开
标题翻译：显示设备
公开(公告)号：JP2011112711A
公开(公告)日：2011-06-09
申请号：JP2009266497
申请日：2009-11-24
申请人： Canon Inc , Hitachi Displays Ltd , キヤノン株式会社 , 株式会社日立ディスプレイズ
发明人： KOTANI YOSHIHIRO , SHIBATA TAKESHI , YAMAMOTO TAKESHI , KODERA KOICHI , ISHII MASAHITO , MANBA NORIO
IPC分类号： G09G3/30 , G09G3/20 , H01L51/50
CPC分类号： G09G3/3233 , G09G2310/0281 , G09G2310/061 , G09G2320/029 , G09G2320/046
摘要： PROBLEM TO BE SOLVED: To provide a display device that can perform measurements in a wider range and detect characteristic changes of a display element with high accuracy while suppressing the increase in circuit size of an inspecting circuit of the element. SOLUTION: The display device includes a plurality of display elements and a characteristic inspecting means that inspects characteristics of current and voltage of the display elements, and the characteristic inspecting means includes a current supply means for supplying an inspecting current to the display element as a target of inspection, a reference voltage output means for outputting a reference voltage, an output voltage-detecting means that detects a code of the voltage of the inspecting target display element relative to the reference voltage each time the reference voltage is output from the reference voltage output means, and an inspection control means that allows the reference voltage output means to sequentially output the reference voltages in response to the codes and acquires a measurement result of the voltage of the inspecting target display element based on the plurality of codes. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以在更宽范围内进行测量并且以高精度检测显示元件的特性变化的显示装置，同时抑制元件的检查电路的电路尺寸的增加。解决方案：显示装置包括多个显示元件和检查显示元件的电流和电压特性的特征检查装置，特征检查装置包括电流供应装置，用于向显示元件提供检查电流作为检查对象，用于输出参考电压的参考电压输出装置，输出电压检测装置，每次从基准电压输出参考电压时，检测目标显示元件的电压相对于参考电压的代码参考电压输出装置，以及检查控制装置，其允许参考电压输出装置响应于代码顺序地输出参考电压，并且基于多个代码获取检查目标显示元件的电压的测量结果。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2004310129A Liquid crystal display device and video signal line driver 有权
公开(公告)号：JP2004310129A
公开(公告)日：2004-11-04
申请号：JP2004177876
申请日：2004-06-16
申请人： Hitachi Device Eng Co Ltd , Hitachi Displays Ltd , Hitachi Ulsi Systems Co Ltd , 日立デバイスエンジニアリング株式会社 , 株式会社日立ディスプレイズ , 株式会社日立超エル・エス・アイ・システムズ
发明人： GOTO MITSURU , KATAYANAGI HIROSHI , OTE YUKIHIDE , SAITO YOSHIYUKI , KODERA KOICHI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To provide a liquid crystal display device and a video signal line driver in which timing margin is secured within a semiconductor integrated circuit that constitutes of a video signal line driving means while latching display data.
SOLUTION: The video signal line driving means has a video signal voltage generating means pair that is provided with a pre-latch section which latches display data, that are made of red, green and blue and are equivalent to one pixel, for equivalent to two pixels, two system bus lines to which the display data equivalent to two pixels are transmitted, a display data switching means which conducts switching and outputs one of the display data equivalent to one pixel outputted from the pre-latch section to one of the two system bus lines and the other display data equivalent to one pixel outputted from the pre-latch section to the other one of the two system bus lines, a positive polarity video signal voltage generating means which receives the display data from one of the two system bus lines and generates positive polarity video signal voltages and a negative polarity video signal voltage generating means which receives the display data from the other two system bus lines and generates negative polarity video signals.
COPYRIGHT: (C)2005,JPO&NCIPI

4. 发明专利

JP2006154855A Liquid crystal display device 审中-公开
标题翻译：液晶显示装置
公开(公告)号：JP2006154855A
公开(公告)日：2006-06-15
申请号：JP2006035345
申请日：2006-02-13
申请人： Hitachi Device Eng Co Ltd , Hitachi Displays Ltd , Hitachi Ulsi Systems Co Ltd , 日立デバイスエンジニアリング株式会社 , 株式会社日立ディスプレイズ , 株式会社日立超エル・エス・アイ・システムズ
发明人： GOTO MITSURU , KATAYANAGI HIROSHI , OTE YUKIHIDE , SAITO YOSHIYUKI , KODERA KOICHI
IPC分类号： G09G3/36 , G02F1/133 , G09G3/20
摘要： PROBLEM TO BE SOLVED: To secure a timing margin when display data are latched in a semiconductor integrated circuit constituting a video signal line driving means even when a clock for display data latching and display data are made high in operating frequency. SOLUTION: The video signal line driving means has a bus line where display data of one pixel consisting of red, green, and blue are transmitted, a negative video signal voltage generating means couple comprising a 1st video signal voltage generating means comprising two positive video signal voltage generating means and one negative video signal voltage generating means and a 2nd video signal voltage generating means comprising one positive video signal voltage generating means and two negative video signal voltage generating means, a means of distributing display data of one pixel transmitted from the bus line to the 1st video signal voltage generating means or 2nd video signal voltage generating means, and a video signal voltage switching means of switching and outputting a pair of video signal voltages outputted from the video signal voltage generating means to a pair of video signal lines. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：即使当显示数据锁存和显示数据的时钟使工作频率高时，也可以在构成视频信号线驱动装置的半导体集成电路中锁存显示数据时确保时序余量。解决方案：视频信号线驱动装置具有发送由红色，绿色和蓝色组成的一个像素的显示数据的总线，负视频信号电压产生装置耦合，包括第一视频信号电压产生装置，包括两个正视频信号电压产生装置和一个负视频信号电压产生装置和第二视频信号电压产生装置，包括一个正视频信号电压产生装置和两个负视频信号电压产生装置，一个分配从一个像素发送的一个像素的显示数据的装置到第一视频信号电压产生装置或第二视频信号电压产生装置的总线;以及视频信号电压切换装置，用于将从视频信号电压产生装置输出的一对视频信号电压切换并输出到一对视频信号线。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005275382A Display device 有权
标题翻译：显示设备
公开(公告)号：JP2005275382A
公开(公告)日：2005-10-06
申请号：JP2005045378
申请日：2005-02-22
申请人： Hitachi Displays Ltd , 株式会社日立ディスプレイズ
发明人： AOKI YOSHINORI , GOTO MITSURU , NAGAO MASASHI , KODERA KOICHI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C11/41
摘要： PROBLEM TO BE SOLVED: To further reduce power consumption in a display device having an SRAM. SOLUTION: A memory cell in a driving circuit comprises a first inverter I1 where an input terminal and an output terminal are connected to a first node and a second node respectively; a second inverter I2 where an output terminal and an input terminal are connected to the first node and the second node, respectively; a first conductive type first transistor M1 which is connected between a first data line DT and the first node, and has a control terminal connected to a first word line W2; a third inverter I3 where the input terminal is connected to the first word line W2; a second conductive type second transistor M3, which is connected between the first data line DT and the first node and has a control terminal connected to the output terminal of the third inverter I3; a first conductive type third transistor M2, which is connected between a second data line DB and the second node and has a control terminal connected to a second word line W1; and a second conductive type fourth transistor M4, which is connected between the second data line W1 and the second node and has a control terminal connected to a third word line W1B. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了进一步降低具有SRAM的显示装置的功耗。解决方案：驱动电路中的存储单元包括第一反相器I1，其中输入端和输出端分别连接到第一节点和第二节点; 第二反相器I2，其中输出端子和输入端子分别连接到第一节点和第二节点; 第一导电型第一晶体管M1，其连接在第一数据线DT与第一节点之间，并且具有连接到第一字线W2的控制端子; 第三反相器I3，其中输入端连接到第一字线W2; 第二导电型第二晶体管M3，连接在第一数据线DT和第一节点之间，并具有连接到第三反相器I3的输出端的控制端; 第一导电型第三晶体管M2，连接在第二数据线DB和第二节点之间，并且具有连接到第二字线W1的控制端子; 以及第二导电型第四晶体管M4，其连接在第二数据线W1和第二节点之间，并且具有连接到第三字线W1B的控制端子。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2010226183A Multi-input single-output circuit and display device 有权
标题翻译：多输入单输出电路和显示设备
公开(公告)号：JP2010226183A
公开(公告)日：2010-10-07
申请号：JP2009068117
申请日：2009-03-19
申请人： Hitachi Displays Ltd , 株式会社日立ディスプレイズ
发明人： SEHATA HIROKO , KODERA KOICHI , KOTANI YOSHIHIRO , MATSUMOTO HIDEICHIRO
IPC分类号： H03F3/34 , G02F1/133 , G09G3/20 , G09G3/36 , H03F3/45
CPC分类号： H03F3/345 , G09G2310/027 , G09G2310/0297 , H03F3/45179
摘要： PROBLEM TO BE SOLVED: To provide a circuit that obtains a more accurate output voltage from a plurality of input voltages. SOLUTION: A two-input single-output circuit 100 includes a current source transistor 110 allowing a predetermined current to flow, a cascade transistor section 120 including two MOS transistors 121 and 122 that are cascade-connected to the drain side of the current source transistor 110 and have the same characteristics, a differential pair section 130 having a first differential pair 131 formed of a first input-side transistor T11 and a first output-side transistor T12 whose source lines are shared and a second differential pair 132 formed of a second input-side transistor T21 and a second output-side transistor T22 whose source lines are shared, and a current mirror circuit section 140. Drain lines of the transistors 121 and 122 of the cascade transistor section 120 are respectively connected to the source lines 133 and 138 of the first differential pair 131 and second differential pair 132. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供从多个输入电压获得更精确的输出电压的电路。解决方案：双输入单输出电路100包括允许预定电流流动的电流源晶体管110，包括两个MOS晶体管121和122的级联晶体管部分120，级联晶体管部分120级联连接到漏极侧电流源晶体管110并具有相同的特性，差分对部分130具有由第一输入侧晶体管T11和源极线共享的第一输出侧晶体管T12和形成的第二差分对132形成的第一差分对131 第二输入侧晶体管T21和源极线共享的第二输出侧晶体管T22以及电流镜电路部140.级联晶体管部分120的晶体管121和122的漏极分别连接到源极第一差分对131和第二差分对132的线133和138。版权所有：（C）2011，JPO＆INPIT

7. 发明专利

JP2004325820A Liquid crystal display device 有权
标题翻译：液晶显示装置
公开(公告)号：JP2004325820A
公开(公告)日：2004-11-18
申请号：JP2003120891
申请日：2003-04-25
申请人： Hitachi Device Eng Co Ltd , Hitachi Displays Ltd , 日立デバイスエンジニアリング株式会社 , 株式会社日立ディスプレイズ
发明人： ITO SHIGERU , MATSUMOTO HIDEICHIRO , OTE YUKIHIDE , KIDA HIDETOSHI , KODERA KOICHI , YAMAMOTO TAKESHI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G09G5/00
CPC分类号： G09G5/006
摘要： PROBLEM TO BE SOLVED: To provide an input circuit is hardly influenced by noise or the like in a liquid crystal display device for transmitting display data by using small amplitude difference signals for a driving circuit for driving a liquid crystal display panel.
SOLUTION: In order to transmit the small amplitude difference signals under the same condition, a small amplitude difference signal line is meanderingly provided such that wiring length becomes the same. In order to reduce influence caused by the overlap of the meandering small amplitude difference signal line and the driving circuit, the input circuit is provided with a level shift circuit and input signals are turned to a stable operation level.
COPYRIGHT: (C)2005,JPO&NCIPI

8. 发明专利

JP2011013335A Display 有权
标题翻译：显示
公开(公告)号：JP2011013335A
公开(公告)日：2011-01-20
申请号：JP2009155719
申请日：2009-06-30
申请人： Hitachi Displays Ltd , 株式会社日立ディスプレイズ
发明人： AKIYAMA KENICHI , KOTANI YOSHIHIRO , SEHATA HIROKO , KODERA KOICHI
IPC分类号： G09G3/36 , G02F1/133 , G09G3/20
CPC分类号： G09G3/20 , G02F1/13306 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To reduce a circuit scale of a decoder circuit outputting a voltage corresponding to an 8-bit digital value.SOLUTION: The decoder circuit 528f outputs a voltage corresponding to a digital value based on a 8-bit digital value and includes: a first decoder circuit 532b and a second decoder circuit 534b which output one voltage respectively using upper-order 6 bits of the 8-bit digital value; a selection circuit 536b which receives voltages output from the first decoder circuit 532b and the second decoder circuit 534b, and distributes the two voltages to three input terminals; and an intermediate voltage output circuit 557 which outputs an intermediate voltage which is one of five intermediate voltages based on the three voltages selected by the selection circuit. The first decoder circuit 532b and the second decoder circuit 534b respectively include a select-switch-type decoder circuit 542 and a tournament-type decoder circuit 544.
摘要翻译：要解决的问题：减少输出对应于8位数字值的电压的解码器电路的电路规模。解码器：解码器电路528f基于8位数字值输出对应于数字值的电压，并且包括：分别使用8位数字值的高位6位输出一个电压的第一解码器电路532b和第二解码器电路534b; 接收从第一解码器电路532b和第二解码器电路534b输出的电压的选择电路536b，并将两个电压分配给三个输入端子; 以及中间电压输出电路557，其基于由选择电路选择的三个电压输出作为五个中间电压中的一个的中间电压。第一解码器电路532b和第二解码器电路534b分别包括选择开关型解码器电路542和比赛型解码器电路544。

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