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1. 发明专利

JP2004318170A Liquid crystal display 有权
公开(公告)号：JP2004318170A
公开(公告)日：2004-11-11
申请号：JP2004177874
申请日：2004-06-16
申请人： Hitachi Device Eng Co Ltd , Hitachi Displays Ltd , Hitachi Ulsi Systems Co Ltd , 日立デバイスエンジニアリング株式会社 , 株式会社日立ディスプレイズ , 株式会社日立超エル・エス・アイ・システムズ
发明人： GOTO MITSURU , KATAYANAGI HIROSHI , OTE YUKIHIDE , SAITO YOSHIYUKI , KODERA KOICHI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To secure a timing margin when display data are latched in a semiconductor integrated circuit constituting a video signal line driving means even when a clock for display data latch and the operating frequency of display data are made fast. SOLUTION: A video signal line driving means has a prelatch part which latches display data of one pixel consisting of red, green, and blue by two pixels, bus lines of two systems to which display data of two pixels are transmitted, and a display data switching means of switching and outputting display data of one pixel outputted from the prelatch part to one of the bus lines of the two systems and display data of the other pixel outputted from the prelatch part to the other bus line. Further, provided are a video signal voltage generating means comprising a positive video signal voltage generating means of inputting display data of one of the two systems of bus lines and generates a positive-polarity video signal voltage and a negative video signal voltage generating means of inputting video data of the other bus line, and generates a negative video signal voltage. COPYRIGHT: (C)2005,JPO&NCIPI

2. 发明专利

JP2004310129A Liquid crystal display device and video signal line driver 有权
公开(公告)号：JP2004310129A
公开(公告)日：2004-11-04
申请号：JP2004177876
申请日：2004-06-16
申请人： Hitachi Device Eng Co Ltd , Hitachi Displays Ltd , Hitachi Ulsi Systems Co Ltd , 日立デバイスエンジニアリング株式会社 , 株式会社日立ディスプレイズ , 株式会社日立超エル・エス・アイ・システムズ
发明人： GOTO MITSURU , KATAYANAGI HIROSHI , OTE YUKIHIDE , SAITO YOSHIYUKI , KODERA KOICHI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To provide a liquid crystal display device and a video signal line driver in which timing margin is secured within a semiconductor integrated circuit that constitutes of a video signal line driving means while latching display data.
SOLUTION: The video signal line driving means has a video signal voltage generating means pair that is provided with a pre-latch section which latches display data, that are made of red, green and blue and are equivalent to one pixel, for equivalent to two pixels, two system bus lines to which the display data equivalent to two pixels are transmitted, a display data switching means which conducts switching and outputs one of the display data equivalent to one pixel outputted from the pre-latch section to one of the two system bus lines and the other display data equivalent to one pixel outputted from the pre-latch section to the other one of the two system bus lines, a positive polarity video signal voltage generating means which receives the display data from one of the two system bus lines and generates positive polarity video signal voltages and a negative polarity video signal voltage generating means which receives the display data from the other two system bus lines and generates negative polarity video signals.
COPYRIGHT: (C)2005,JPO&NCIPI

3. 发明专利

JP2006154855A Liquid crystal display device 审中-公开
标题翻译：液晶显示装置
公开(公告)号：JP2006154855A
公开(公告)日：2006-06-15
申请号：JP2006035345
申请日：2006-02-13
申请人： Hitachi Device Eng Co Ltd , Hitachi Displays Ltd , Hitachi Ulsi Systems Co Ltd , 日立デバイスエンジニアリング株式会社 , 株式会社日立ディスプレイズ , 株式会社日立超エル・エス・アイ・システムズ
发明人： GOTO MITSURU , KATAYANAGI HIROSHI , OTE YUKIHIDE , SAITO YOSHIYUKI , KODERA KOICHI
IPC分类号： G09G3/36 , G02F1/133 , G09G3/20
摘要： PROBLEM TO BE SOLVED: To secure a timing margin when display data are latched in a semiconductor integrated circuit constituting a video signal line driving means even when a clock for display data latching and display data are made high in operating frequency. SOLUTION: The video signal line driving means has a bus line where display data of one pixel consisting of red, green, and blue are transmitted, a negative video signal voltage generating means couple comprising a 1st video signal voltage generating means comprising two positive video signal voltage generating means and one negative video signal voltage generating means and a 2nd video signal voltage generating means comprising one positive video signal voltage generating means and two negative video signal voltage generating means, a means of distributing display data of one pixel transmitted from the bus line to the 1st video signal voltage generating means or 2nd video signal voltage generating means, and a video signal voltage switching means of switching and outputting a pair of video signal voltages outputted from the video signal voltage generating means to a pair of video signal lines. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：即使当显示数据锁存和显示数据的时钟使工作频率高时，也可以在构成视频信号线驱动装置的半导体集成电路中锁存显示数据时确保时序余量。解决方案：视频信号线驱动装置具有发送由红色，绿色和蓝色组成的一个像素的显示数据的总线，负视频信号电压产生装置耦合，包括第一视频信号电压产生装置，包括两个正视频信号电压产生装置和一个负视频信号电压产生装置和第二视频信号电压产生装置，包括一个正视频信号电压产生装置和两个负视频信号电压产生装置，一个分配从一个像素发送的一个像素的显示数据的装置到第一视频信号电压产生装置或第二视频信号电压产生装置的总线;以及视频信号电压切换装置，用于将从视频信号电压产生装置输出的一对视频信号电压切换并输出到一对视频信号线。版权所有（C）2006，JPO＆NCIPI

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