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1. 发明专利

JP2012247300A Position measurement system 有权
标题翻译：位置测量系统
公开(公告)号：JP2012247300A
公开(公告)日：2012-12-13
申请号：JP2011119072
申请日：2011-05-27
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： KAWAGUCHI HIROSHI , YOSHIMOTO MASAHIKO , SODA SHINPEI , TAKAGI TOMOYA , IZUMI SHINTARO
IPC分类号： G01S5/28
摘要： PROBLEM TO BE SOLVED: To provide a position measurement system for measuring the position of a terminal more highly accurately than a conventional technology.SOLUTION: A position measurement system includes a control part for, by using a microphone array network system in which a plurality of nodes having a microphone array are connected and time-synchronized via a network, estimating the position of each node. Each node includes: a sound source estimation processing part for, on the basis of a sound signal from one node received by the microphone array, estimating the angle of the direction of arrival of the sound signal; a distance estimation part for estimating a distance from the node which has transmitted the sound signal on the basis of a difference between the transmission time and reception time of the sound signal and the speed of the sound signal; and a data communication part for transmitting and receiving the estimated angle of the direction of arrival and the estimated distance with respect to the other nodes by data communication. The control part is configured to estimate and calculate the position of each node on the basis of the estimated angle of the direction of arrival and the estimated distance.
摘要翻译：要解决的问题：提供一种比常规技术更高精度地测量端子位置的位置测量系统。解决方案：位置测量系统包括控制部件，用于通过使用麦克风阵列网络系统，其中具有麦克风阵列的多个节点经由网络连接并且经时间同步，估计每个节点的位置。每个节点包括：声源估计处理部分，用于根据由麦克风阵列接收的一个节点的声音信号估计声音信号的到达方向的角度; 距离估计部，其基于声音信号的发送时间和接收时间之间的差与声音信号的速度来估计从发送了声音信号的节点的距离; 以及数据通信部，用于通过数据通信发送和接收相对于其他节点的到达方向的估计角度和估计距离。控制部被配置为基于到达方向的估计角度和估计距离来估计和计算每个节点的位置。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2012253612A Flip-flop circuit device and processor device using the same 有权
标题翻译： FLIP-FLOP电路装置和使用其的处理器装置
公开(公告)号：JP2012253612A
公开(公告)日：2012-12-20
申请号：JP2011125500
申请日：2011-06-03
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： KAWAGUCHI HIROSHI , YOSHIMOTO MASAHIKO , KUGATA KOJI , TAKAGI TOMOYA , NOGUCHI HIROKI
IPC分类号： H03K3/356 , H03K3/3562
摘要： PROBLEM TO BE SOLVED: To provide a flip-flop circuit and a processor device therewith which operate more stably on a low voltage than before.SOLUTION: A flip-flop circuit device includes: a first flip-flop circuit including a first latch circuit and a second latch circuit; and a second flip-flop circuit including a third latch circuit and a fourth latch circuit. In a first voltage mode of operation on a first operating voltage, gates connecting internal nodes of the first and second flip-flop circuits are opened, so that the first flip-flop circuit and the second flip-flop circuit operate individually. In a second voltage mode of operation on a second operating voltage lower than the first operating voltage, on the other hand, the gates are short-circuited, so that the first flip-flop circuit and the second flip-flop circuit hold data in an inverse relationship and cooperate to perform complementary data processing.
摘要翻译：要解决的问题：提供一种触发器电路及其处理器装置，其操作在比以前更低的电压下更稳定。解决方案：触发器电路装置包括：第一触发器电路，包括第一锁存电路和第二锁存电路; 以及包括第三锁存电路和第四锁存电路的第二触发器电路。在第一工作电压的第一电压操作模式下，连接第一和第二触发器电路的内部节点的栅极被打开，使得第一触发器电路和第二触发器电路分别工作。另一方面，在低于第一工作电压的第二工作电压的第二电压工作模式下，栅极被短路，使得第一触发器电路和第二触发器电路将数据保存在反向关系并配合进行互补数据处理。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012244199A Operational-amplifier-less/capacitor-less ad converter and td converter 审中-公开
标题翻译：运算放大器无电容电容器AD转换器和TD转换器
公开(公告)号：JP2012244199A
公开(公告)日：2012-12-10
申请号：JP2011108910
申请日：2011-05-14
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： KAWAGUCHI HIROSHI , YOSHIMOTO MASAHIKO , KONISHI KEITA , IZUMI SHINTARO
IPC分类号： H03M1/50
CPC分类号： H03M1/50 , H03M3/416
摘要： PROBLEM TO BE SOLVED: To provide an operational-amplifier-less/capacitor-less AD converter that implements higher order noise shaping by propagating a quantization error while utilizing a noise shaping characteristic of a GROTDC (Gated Ring Oscillator Time to Digital Converter).SOLUTION: The operational-amplifier-less/capacitor-less AD converter includes: a VT conversion circuit section for receiving an analog input voltage and a sampling clock, converting the analog input voltage to a corresponding delay time and outputting time domain data; GRO circuit sections in N stages (N is more than one) for receiving the time domain data; error propagation circuit sections each inserted between the preceding GRO and the following GRO to propagate an output oscillation waveform of the preceding GRO including a quantization error; reset sections each for resetting each corresponding error propagation circuit section and counter circuit section on the sampling clock; counter circuit sections each for measuring the number of waves of the output oscillation waveform of each corresponding GRO; and an output signal generation section for generating an output signal from output count values of the counter circuits.
摘要翻译：要解决的问题：提供一种运算放大器/无电容器的AD转换器，其通过传播量化误差来实现更高阶的噪声整形，同时利用GROTDC（门控振荡器时间到数字转换器）的噪声整形特性）。解决方案：无运算放大器/无电容器AD转换器包括：VT转换电路部分，用于接收模拟输入电压和采样时钟，将模拟输入电压转换为相应的延迟时间并输出时域数据 ; 用于接收时域数据的N级的GRO电路部分（N个多于一个）; 每个插入前面的GRO和随后的GRO之间的误差传播电路部分传播包括量化误差的前面的GRO的输出振荡波形; 每个复位部分用于复位采样时钟上的每个对应的误差传播电路部分和计数器电路部分; 每个用于测量每个对应的GRO的输出振荡波形的波数的计数器电路部分; 以及输出信号生成部分，用于从计数器电路的输出计数值产生输出信号。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2012174317A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2012174317A
公开(公告)日：2012-09-10
申请号：JP2011037109
申请日：2011-02-23
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： KAWAGUCHI HIROSHI , YOSHIMOTO MASAHIKO , NOGUCHI HIROKI , TAKAGI TOMOYA , KUGATA KOJI , OKUMURA SHUNSUKE
IPC分类号： G11C11/413 , G11C11/41 , G11C11/412
摘要： PROBLEM TO BE SOLVED: To provide a multi-port semiconductor storage device important in signal processing.SOLUTION: A semiconductor storage device comprises a memory cell including: a latch circuit comprised of a cross-coupled inverter having two data holding nodes connected to a first bit line; a first switch part provided between the first bit line and each of the data holding nodes of the inverter; and a first word line for controlling the conduction of the first switch part. It also comprises: a second switch part for switching between a first mode, in which respective data holding nodes of a plurality of memory cells are separated for each memory cell and one bit is comprised of one memory cell, and a second mode, in which the respective data holding nodes of the plurality of memory cells are connected in parallel and one bit is comprised of the plurality of memory cells; and further, a third switch part for switching between whether or not to connect one data holding node of the respective data holding nodes of the plurality of memory cells to a second bit line.
摘要翻译：要解决的问题：提供在信号处理中重要的多端口半导体存储装置。解决方案：一种半导体存储装置，包括：存储单元，包括：锁存电路，包括具有连接到第一位线的两个数据保持节点的交叉耦合的反相器; 第一开关部分，设置在逆变器的第一位线和每个数据保持节点之间; 以及用于控制第一开关部件的导通的第一字线。它还包括：用于在第一模式之间进行切换的第二开关部件，其中，针对每个存储器单元分离多个存储器单元的各个数据保持节点和一个位的第一模式由一个存储单元组成，第二模式包括：多个存储单元的相应数据保持节点并联连接，一位由多个存储单元构成; 以及第三开关部分，用于在是否将多个存储器单元的各个数据保持节点的一个数据保持节点连接到第二位线之间进行切换。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2009116729A Image processor and processing method 有权
标题翻译：图像处理器和处理方法
公开(公告)号：JP2009116729A
公开(公告)日：2009-05-28
申请号：JP2007290751
申请日：2007-11-08
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： MATSUDA YOSHIO , ISHIHARA HAJIME , MIYAMA MASAYUKI , KAWAGUCHI HIROSHI , YOSHIMOTO MASAHIKO
IPC分类号： G06T7/20
摘要： PROBLEM TO BE SOLVED: To provide an image processor and processing method, allowing computation at a computation time shorter compared with that in the prior art, in the computation of an optical flow. SOLUTION: An OPF computation processor 20 includes a PIC computation circuit 25 for generating a hierarchical image data by carrying out sampling and filtering for image data of two frames, and an OPF computation circuit 30 (including computation circuits 28, 29) for computing a spatial brightness gradient matrix and a mismatch vector, based on the generated hierarchical image data, and for computing the optical flow, based on the computed spatial brightness gradient matrix and the mismatch vector. The OPF computation circuit 30 computes the optical flow, while repeating four pixel values within an area including four pixels adjacent each other, in a prescribed pixel order using those as a unit, as to an area adjacent to the area. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种图像处理器和处理方法，在计算光流时，允许在计算时间比现有技术更短的计算时间进行计算。解决方案：OPF计算处理器20包括PIC计算电路25，用于通过对两帧的图像数据进行采样和滤波来生成分层图像数据;以及OPF计算电路30（包括计算电路28,29），用于基于生成的分层图像数据计算空间亮度梯度矩阵和失配向量，并且基于所计算的空间亮度梯度矩阵和失配向量来计算光流。 OPF计算电路30计算光流，同时在与该区域相邻的区域中以规定的像素顺序重复包括彼此相邻的四个像素的区域内的四个像素值。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2006060939A Output variable type power supply circuit 有权
标题翻译：输出可变型电源电路
公开(公告)号：JP2006060939A
公开(公告)日：2006-03-02
申请号：JP2004241356
申请日：2004-08-20
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： SAKURAI TAKAYASU , KAWAGUCHI HIROSHI , ONIZUKA KOHEI
IPC分类号： H02M3/155 , G05F1/56 , H02M3/07
CPC分类号： H02M3/158 , H02M3/156
摘要： PROBLEM TO BE SOLVED: To provide an output variable type power supply circuit that can change a voltage of a voltage output node of a power supply circuit at high speed when lowering an output of the power supply circuit to a low voltage from a high voltage, and when raising the output to a high voltage from a low voltage.
SOLUTION: The output variable type power supply circuit comprises the power supply circuit 10 that is connected to a voltage source 11, and outputs voltages of n-kinds of different values from the voltage output node 12 according to a control signal; a first switch element 13 connected between the voltage output node 12 and a reference voltage node; a second switch element 14 connected between the voltage output node 12 and the voltage source 11; and a control circuit that makes the first switch element 13 conductive when the power supply circuit 10 changes a voltage of the voltage output node 12 to a second voltage lower than a first voltage from the first voltage, and makes the second switch element 14 conductive when the power supply circuit 10 changes the voltage of the voltage output node 12 to a first voltage lower than a second voltage form the second voltage.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种输出可变型电源电路，其可以在将电源电路的输出从低电压降低到低电压时，高电平地改变电源电路的电压输出节点的电压高电压时，并将输出从低电压提高到高电压。
解决方案：输出可变型电源电路包括连接到电压源11的电源电路10，并根据控制信号从电压输出节点12输出不同值的n种电压; 连接在电压输出节点12和参考电压节点之间的第一开关元件13; 连接在电压输出节点12和电压源11之间的第二开关元件14; 以及当电源电路10将电压输出节点12的电压从第一电压变为低于第一电压的第二电压时，使第一开关元件13导通的控制电路，并且使第二开关元件14导通，电源电路10将电压输出节点12的电压从第二电压变为低于第二电压的第一电压。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2006059468A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2006059468A
公开(公告)日：2006-03-02
申请号：JP2004241357
申请日：2004-08-20
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： SAKURAI TAKAYASU , KAWAGUCHI HIROSHI , FAYEZ ROBERT SALIBA
IPC分类号： G11C11/413
CPC分类号： G11C11/413
摘要： PROBLEM TO BE SOLVED: To secure such a feature that voltage of word line is started after voltage of power source line attains high voltage first of all at every position, when a row of cell array is selected. SOLUTION: This device is provided with: a plurality of SRAM cells 11 arranged in a matrix; the word lines WL connected in common with respect to the plurality of SRAM cells arranged on each row; the power source lines PL connected in common with respect to the plurality of SRAM cells arranged on each row; and a power source line/word line control circuit 13 for operating in such a manner that the voltage of the power source lines PL is raised when accessing the plurality of SRAM cells for every row and the activation of the word lines is started after the voltage of the power source lines attains the high voltage DDH at every position, and the word lines are inactivated when shifting to the non-access state from the access state and the voltage of the power sources lines is made to change to the low voltage DDL after the voltage of the power source lines is changed to a ground voltage GND at every position. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了确保当选择一行单元阵列时，在电源线的电压在每个位置首先达到高电压之后开始字线电压的这种特征。解决方案：该装置设置有：以矩阵形式布置的多个SRAM单元11; 字线WL相对于布置在每行上的多个SRAM单元共同连接; 电源线PL相对于布置在每行上的多个SRAM单元共同连接; 以及电源线/字线控制电路13，其以这样的方式操作，即当访问每行的多个SRAM单元时电源线PL的电压升高，并且在电压之后开始字线的激活的电源线在每个位置达到高电压DDH，并且在从访问状态转移到非访问状态时字线被去激活，并且使电源线的电压变为低电压DDL之后电源线的电压在每个位置变为接地电压GND。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2013004110A Semiconductor storage device for reducing charge and discharge power of writing bit-line 审中-公开
标题翻译：半导体存储器件，用于降低写入位线的充电和放电功率
公开(公告)号：JP2013004110A
公开(公告)日：2013-01-07
申请号：JP2011130757
申请日：2011-06-11
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： YOSHIMOTO MASAHIKO , KAWAGUCHI HIROSHI , YOSHIMOTO SHUSUKE
IPC分类号： G11C11/413 , G11C11/41
CPC分类号： G11C11/419
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of solving a half-select problem in an 8Tr SRAM and simultaneously achieving charge and discharge power reduction in a half-select column being a problem in a conventional write-back method.SOLUTION: The 8Tr SRAM includes 1) a bit-line half driving circuit which can read holding data from a reading bit-line (RBL) of each memory cell of a memory cell group in a column direction and drives a writing bit-line only in a memory cells of half-select columns in accordance with the read data, 2) a selection signal circuit for inputting an enable signal (DRN) and a column selection signal (CLE) of a bit-line half driving circuit to activate the bit-line half driving circuit, and 3) an equalizer circuit which equalizes a writing bit-line of a memory cell group in the column direction and does not perform precharge the writing bit-line.
摘要翻译：要解决的问题：提供一种半导体存储装置，其能够解决8Tr SRAM中的半选择问题，并且同时实现在常规回写方法中的问题的半选择列中的充电和放电功率降低。解决方案：8Tr SRAM包括1）位线半驱动电路，其可以从列方向上的存储器单元组的每个存储单元的读取位线（RBL）读取保持数据，并驱动写入位仅在根据读取数据的半选择列的存储单元中存储线; 2）选择信号电路，用于将位线半驱动电路的使能信号（DRN）和列选择信号（CLE）输入到激活位线半驱动电路，以及3）均衡电路，其对列方向上的存储单元组的写位线进行均衡，并且不对写位线执行预充电。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2014003580A Td converter and ad converter 有权
标题翻译： TD转换器和AD转换器
公开(公告)号：JP2014003580A
公开(公告)日：2014-01-09
申请号：JP2012203662
申请日：2012-09-14
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： KAWAGUCHI HIROSHI , YOSHIMOTO MASAHIKO , KONISHI KEITA , IZUMI SHINTARO , OKUNO KEISUKE
IPC分类号： H03M1/50
CPC分类号： H03M1/50 , G04F10/005
摘要： PROBLEM TO BE SOLVED: To provide a high resolution, operational-amplifier-less/capacitor-less TD converter that reduces a switching loss and dispenses with statically holding phase information.SOLUTION: The TD converter includes: an oscillation circuit section 1 fed with time domain data; a High counter circuit section 3 for measuring a wave number of an output oscillation waveform of the oscillation circuit section while the time domain data is "High," and a Low counter circuit section 4 for measuring a wave number of the output oscillation waveform of the oscillation circuit section while the time domain data is "Low"; an output signal generation section 5 for generating an output signal from output count values of the High counter circuit section 3 and the Low counter circuit section 4; and a frequency control circuit 2 capable of causing the oscillation circuit section to oscillate continuously and controlling the oscillation frequency.
摘要翻译：要解决的问题：提供一种降低开关损耗并省去静态保持相位信息的高分辨率，无运算放大器/无电容器的TD转换器。解决方案：TD转换器包括：馈送时间的振荡电路部分1 域数据; 用于测量时域数据为“高”的振荡电路部分的输出振荡波形的波数的高计数器电路部分3和用于测量输出振荡波形的波数的低计数器电路部分4 振荡电路部分，而时域数据为“低”; 输出信号生成部分5，用于从高计数器电路部分3和低计数器电路部分4的输出计数值产生输出信号; 以及能够使振荡电路部连续振荡并控制振荡频率的频率控制电路2。

10. 发明专利

JP2013030946A Sensor network system and communication method therefor 有权
标题翻译：传感器网络系统及其通信方法
公开(公告)号：JP2013030946A
公开(公告)日：2013-02-07
申请号：JP2011164986
申请日：2011-07-28
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： KAWAGUCHI HIROSHI , YOSHIMOTO MASAHIKO , IZUMI SHINTARO
IPC分类号： H04R3/00 , H04R1/40
CPC分类号： H04R3/005 , G10L2021/02166 , H04R1/406 , H04R2201/401
摘要： PROBLEM TO BE SOLVED: To enable efficient data aggregation in a sensor network system to greatly reduce network traffic.SOLUTION: The sensor network system includes a plurality of nodes having known position information interconnected by a network through propagation paths, and collects data measured in each node to aggregate to one base station. In the sensor network system, a base station calculates the position of a signal source, on the basis of an angle estimation value of a signal from each node and the position information of each node; designates a node nearest to the signal source as a cluster head node; transmits the position of the signal source and information on the cluster head node to each node to cluster each node located within a certain number of hops from each cluster head node, as a node subordinate to each cluster; and performs emphasis processing on a signal received by a sensor array for each node subordinate to the designated cluster, to transmit it to the base station.
摘要翻译：要解决的问题：为了在传感器网络系统中实现有效的数据聚合，以大大减少网络流量。解决方案：传感器网络系统包括具有通过传播路径由网络互连的已知位置信息的多个节点，并且收集在每个节点中测量的数据以聚合到一个基站。在传感器网络系统中，基站根据来自各节点的信号的角度估计值和各节点的位置信息来计算信号源的位置; 指定最靠近信号源的节点作为簇头节点; 将信号源的位置和簇头节点上的信息发送到每个节点，将位于每个簇头节点的特定跳数内的每个节点聚类成从属于每个簇的节点; 并且对由传感器阵列接收到的指示簇下属的每个节点的信号执行加重处理，以将其发送到基站。版权所有（C）2013，JPO＆INPIT

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