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1. 发明专利

JPS6299979A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6299979A
公开(公告)日：1987-05-09
申请号：JP23740985
申请日：1985-10-25
申请人： HITACHI VLSI ENG , HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TACHIMORI HIROSHI , FUKUDA HIROSHI , FUKAZAWA TAKESHI , IWAGAMI FUMIO , SASAKI KATSURO
IPC分类号： G11C11/417 , G11C11/34 , G11C11/413
摘要： PURPOSE:To reduce the necessary number of current limiting elements so as to make the ratio of the occupying area of the current limiting elements to the whole are of a chip smaller, by commonly using the current limiting elements against common data lines. CONSTITUTION:A pair of data lines Da and Da' (Db and Db') corresponding to each row of memory mats Ma (Mb) is connected with common data lines CDa and CDa' (CDb and CDb') through a data line selecting MOSFET Qa (Qb). A bias circuit 7 which sets the bias potential of the common data lines to a prescribed level at which a sense amplifier 3a (3b) can operate with high sensitivity, is provided with common data line load MOSFETs Qa5 and Qa6 (Qb5 and Qb6) connected between the common data lines and a power supply terminal VCC, pull-down MOSFETs Qa7 and Qa8 (Qb7 and Qb8) connected to the common data lines, and a current limiting MOSFET Q9 commonly connected with the source and earth terminal of each pull-down MOSFET.

2. 发明专利

JPS61294682A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61294682A
公开(公告)日：1986-12-25
申请号：JP13416085
申请日：1985-06-21
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： UCHIBORI KIYOBUMI , NAKAMURA HIDEAKI , TACHIMORI HIROSHI
IPC分类号： G11C11/34
摘要： PURPOSE:To reduce noises of a RAM and to speed up its operation by putting a voltage detecting circuit in operation with a change detection pulse for an address signal and providing a couple of MOSFETs which charge the output terminal of a buffer circuit to an intermediate level by the output of the voltage detecting circuit. CONSTITUTION:When even one address signal varies, a circuit ATD generates the inversion of phiq in response and phiq' goes up to H, so that a clocked inverter IV operates. When the parasitic capacitance at the output terminal Dout of the buffer is held at H, the IV 1 outputs H and an IV 2 outputs L to turn on a FET Q19, thereby discharging the parasitic capacitance gradually. When the parasitic capacitance is held at L, the VI 1 outputs H and the VI 2 outputs L to turn on a Q18, thereby charging the parasitic capacitance gradually. The Dout is discharged to an intermediate level between H and L within the width of the pulse phiq', i.e. the operation period of the IVs 1 and 2 and then a readout signal is applied to gates of Q16 and Q17 to obtain an output signal. In this case, the output buffer generate varies from the intermediate level to H or L, so the output level is determined at a high speed in a small-noise state.

3. 发明专利

JPS6299984A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6299984A
公开(公告)日：1987-05-09
申请号：JP23740885
申请日：1985-10-25
申请人： HITACHI VLSI ENG , HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TACHIMORI HIROSHI , FUKAZAWA TAKESHI , IWAGAMI FUMIO , HATAKEYAMA AKIYOSHI , TAKAHASHI OSAMU
IPC分类号： G11C11/413 , G11C11/34 , G11C11/401 , G11C11/403 , G11C11/409
摘要： PURPOSE:To prevent occurrence of a through current at an input first-stage circuit when shifting to battery backup, by providing an input first-stage controlling means which forces the output level of the input first-stage circuit to a low level in accordance with a change in a supply voltage. CONSTITUTION:The output Vout of the supply voltage detecting circuit 7 of an input first-stage controlling means 1 becomes low in level when a supply voltage becomes lower than the lower limit value of the voltage of a system power source. A control signal (phi) outputted from a gate circuit 10 composed of an inverter circuit 8 and NOR gate circuit 9 becomes high in level when a chip select signal, the inverse of CS is high and the output Vout is low. When the control signal (phi) becomes high in level, MOSFETs Q5 and Q6 constituting an input means circuit 2 are respectively turned off and turned on and MOSFETs Q3 and Q4 are cut off from each other and, accordingly, an output terminal dout is forced to a grounding level. Therefore, even when such a signal of an intermediate value level that is inputted at the time when shifting to battery backup is inputted to the input terminal din of the circuit 2, no through current is produced at the point first-stage circuit 2.

4. 发明专利

JPS60123053A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60123053A
公开(公告)日：1985-07-01
申请号：JP22992783
申请日：1983-12-07
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： AKIMA ISAO , TACHIMORI HIROSHI , TAKAHASHI OSAMU , FUKUDA HIROSHI
IPC分类号： H01L27/08 , H01L27/092 , H01L29/78
摘要： PURPOSE:To stabilize the potential of the central section of an MOSFET or the whole substrate and well potential, to reduce the resistance of a parasitic thyristor and to prevent a latch-up by forming an electrical supply section at the central section of the MOSFET or a position in the vicinity of the central section and applying the same supply signal as an electrical supply section in a peripheral section to the electrical supply section. CONSTITUTION:A P type well 11 is formed to one part of an N type silicon substrate 10, a PMOSFETQ'P is constituted on the main surface of the substrate 10 and an NMOSFETQ'N on the P type well 11, and a CMOS circuit is formed by these transistors. Consequently, electrical supplies to the substrate and the well are also executed at the central section by both sides and electrical supply sections 16, 24 in the PMOSQ'P and the NMOSQ'N. As a result, the floating of substrate potential in the central sections of the P and NMOSs and well potential is prevented, and substrate potential in the whole regions of each MOS and well potential are each stabilized at potential of VDD and VSS. Accordingly, substantial base resistance is reduced, the operation of thyristors by transistors TR'1, TR'2 is difficult to be generated, and the generation of a latch-up phenomenon can be prevented.

5. 发明专利

JPS6226692A STATIC TYPE RAM 失效
公开(公告)号：JPS6226692A
公开(公告)日：1987-02-04
申请号：JP16417485
申请日：1985-07-26
申请人： HITACHI VLSI ENG , HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TACHIMORI HIROSHI , FUKAZAWA TAKESHI , OOKUBO CHIKAO , FUKUDA HIROSHI , HATAKEYAMA AKIYOSHI
IPC分类号： G11C11/41 , G11C11/34
摘要： PURPOSE:To speed up an operation by providing an MOSFET for equalizing which is made to on state by the non-selective level of a selection signal supplied to a column switch MOSFET that connects a complementary data line to a common complementary data line. CONSTITUTION:When the complementary data lines of MOSFETs Q16, Q17 are made to the non-selective state by the supply of data line selection signals Y0, Y1 corresponding to the gates, Q16, Q17 are made to on state which corresponding column switches MOSFET Q12, Q13 and Q14, Q15 are made to off state, and equalizing is executed making complementary data lines D0, the inverse of D0 and D1, the inverse of D1 short-circuited state. Consequently, in the chip selection state to which address signals AX, AY are supplied, the level of complementary data lines D, the inverse of D connected to a memory cell according to actual selection timing of the memory cell, changes from level equal to each other according to memory information of the memory cell in case of reading operation, and changes according to writing signals in case of writing operation. Accordingly, the speeding up of the operation becomes possible.

6. 发明专利

JPS60167467A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60167467A
公开(公告)日：1985-08-30
申请号：JP2179084
申请日：1984-02-10
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： FUKUDA HIROSHI , TACHIMORI HIROSHI , TAKAHASHI OSAMU
IPC分类号： H01L29/78
摘要： PURPOSE:To enlarge the diffused layer surrounded by a gate electrode, and to prevent the lack of gate insulation film in the photoetching process by a method wherein the gate electrode is shaped into a square framelike form, and a corner of the gate electrode is bent at an angle of 90 deg. or more to a straight line section of the gate electrode. CONSTITUTION:The gate electrode 31 forms almost a square frame and locates one side 41 on an SiO2 layer 32 and the other side 42 in a P-well 30. The reason why one side 41 is located on the layer 32 is to improve the static withstand voltage by taking the area of the diffused layer 35 on the side of an input circuit occupied in the well 30 as wide as possible. Besides, formation of the gate electrode 31 in square frame like form is likewise to take wider the area of the layer 35 in the well 30. The corners 43 and 44 of the gate electrode 31 are bent at an angle of 90 deg. or more to the straight line sections 41, 42, 45, and 46, thus improving the adhesion property with photo resist.

7. 发明专利

JPS6083290A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6083290A
公开(公告)日：1985-05-11
申请号：JP19077183
申请日：1983-10-14
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TACHIMORI HIROSHI , FUKUDA HIROSHI , ADACHI KOUICHI , AOTO TOSHIROU , TAKAHASHI OSAMU
IPC分类号： G11C11/419 , G11C11/34
摘要： PURPOSE:To realize a high-sensitivity, high-gain sense amplifier of extremely simple constitution by combining a differential amplifying MOSFET with an MOSFET provided to its drain for latch formation, and utilizing their positive feedback operation. CONSTITUTION:Differential amplifying MOSFETs Q20 and Q21 are composed of n channel MOSFETs. Further, p channel MOSFETs Q22 and Q22 in latch form are provided as their load means. Further, an n channel MOSFETQ24 which receives an internal control signal phis generated on the basis of a timing signal generated by an edge trigger circuit EGT and a chip selection signal ce during address signal variation is provided at the common source of the differential amplifying MOSFETs Q20 and Q21 so as to reset the latch during the address signal variation and also reduce the current consumption during nonselection, thereby controlling its operation timing. Consequently, an input signal IN is amplified with a high gain and at a high speed.

8. 发明专利

JPS59231847A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS59231847A
公开(公告)日：1984-12-26
申请号：JP10571383
申请日：1983-06-15
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： AKIMA ISAO , FUKUDA HIROSHI , OOKUBO KIYOUO , ADACHI KOUICHI , TACHIMORI HIROSHI
IPC分类号： H01L29/78 , H01L27/02 , H01L27/06
摘要： PURPOSE:To assure the protection of a gate insulating film by a method wherein an IC with an input protecting circuit between an input terminal and an internal circuit is composed of an electric resistor with a protecting circuit series-inserted thereinto and a clamp element with the protecting circuit parallel-inserted thereinto while the clamp elemnt is composed of a parasitic MOSFET provided underneath the resistor serving both as a gate electrode of this FET. CONSTITUTION:An electric resistor Ri with a protecting circuit series-inserted thereinto and a clamp element Q1 with the protecting circuit parallel-inserted thereinto comprising MOSFET element are provided between an input terminal pad IN and an internal circuit IC. In other words, source and drain regions 12 are diffusion-formed on the surface layer of a semiconductor substrate 10 and the gaps between the regions 12 are covered with a thick insulating film 14 and the overall surface of the film 14 is further covered with another insulating film 16. Next a resistor Ri comprising multicrystal-line Si is provided on the film 16 located between the regions 12 while a parasitic MOSFET element Q1 is composed of the insulating film 14 and the gate insulating film 16. Through these procedures, the drain region D and the resistor Ri to be a gate electrode in the regions 12 are connected to the internal circuit IC while the source region S is grounded.

9. 发明专利

JPS61219955A PHOTOMASK 失效
公开(公告)号：JPS61219955A
公开(公告)日：1986-09-30
申请号：JP6063485
申请日：1985-03-27
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： FUKUDA HIROSHI , TACHIMORI HIROSHI , KUNIMOTO YUKINORI , ADACHI KOICHI
IPC分类号： G03F1/00 , G03F1/54 , H01L21/027
摘要： PURPOSE:To prevent the breakdown of a metallic film pattern of a photomask by forming a corner part of a semiconductor area, to an obtuse angle or a circular arc shape so that a distance between each semiconductor area becomes larger than a prescribed value, and using the photomask of the metallic film pattern. CONSTITUTION:In a semiconductor substrate consisting of an (n )-type single crystal silicon, a field insulating film is formed on a main surface on the substrate by using a photomask 22. This photomask 22 is used for a negative type photoresist by forming a chrome thin film 23 in a rectangular shape on a quartz substrate. In this regard, in accordance with the shape of the chrome thin film 23, a field insulating film is formed on the semiconductor substrate. A corner part 23A of this chrome thin film 23 is formed in a circular arc shape. This circular arc shape is formed so that a distance between each semiconductor area becomes larger than a prescribed value. Accordingly, when the photomask has been set to an exposing device, a corner part of a metallic pattern causes no melt breakdown, and a drop of the yield can be prevented.

10. 发明专利

JPS60242580A MOS STATIC TYPE RAM 失效
公开(公告)号：JPS60242580A
公开(公告)日：1985-12-02
申请号：JP9653484
申请日：1984-05-16
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TACHIMORI HIROSHI , FUKUDA HIROSHI
IPC分类号： G11C11/41 , G11C11/34
摘要： PURPOSE:To obtain a MOS static RAM with high reliability by providing a function which stops selectively the equalizing operation of complementary data lines with a signal from an external terminal and stopping the equalizing operation during a test of operation, etc. CONSTITUTION:A write enable signal WE' supplied from the external terminal is supplied to the gate of a MOSFETQ12. A gate insulating film is used as a field insulating film so as to make the threshold voltage of the Q12 higher than a source voltage VCC, and a MOSFETQ11 is provided as a load between its drain and the source voltage VCC. The drain output of the Q12 is sent as a control signal to an AND gate AND. When the write enable signal WE' goes up to a high level, the Q12 turns on and generates a low-level drain output, and the AND gate is closed to stop equalizing pulses phia. Consequently, a function test is taken on severe operation condition, so the high-reliability MOS static RAM is obtained.

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