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1. 发明专利

JPH1039836A LED DISPLAY AND MONITORING METHOD FOR ITS LIFETIME 失效
公开(公告)号：JPH1039836A
公开(公告)日：1998-02-13
申请号：JP19759496
申请日：1996-07-26
申请人： HITACHI LTD , YAMATAKE HONEYWELL CO LTD
发明人： ONISHI HIDEO , SUZUKI OSAMU , KOIWAI JUICHI , ISHIKAWA HARUO , TAKAHASHI MAKOTO
IPC分类号： G09G3/32
摘要： PROBLEM TO BE SOLVED: To provide a LED display which can predict self life-time by informing a user of the finish of a lifetime of a LED when a lighting time that is integrated during the lighting of a LED reaches a lifetime previously set. SOLUTION: A LED display 1 is provided with a LED 11, a LED protection resistor 12, a display circuit 14, and a lighting current is controlled constant by a power source stabilizing device and a current detector 13. Further, the display 1 is provided with a memory 17 storing a lifetime of the LED 11 previously set and an integrated lighting time updated by integration, a CPU 15 discriminating whether the integrated lighting time reaches the lifetime or not, and a transmitting device 16 outputting lifetime reaching information to a monitoring side controller 100, then unit constitution is performed.

2. 发明专利

JPH1042378A I/O DEVICE AND CENTRALIZED MONITORING SYSTEM 失效
公开(公告)号：JPH1042378A
公开(公告)日：1998-02-13
申请号：JP19759296
申请日：1996-07-26
申请人： HITACHI LTD , YAMATAKE HONEYWELL CO LTD
发明人： SUZUKI OSAMU , ONISHI HIDEO , KOIWAI JUICHI , TSUTSUMI HIROAKI , TAKAHASHI MAKOTO
IPC分类号： H04Q9/00
摘要： PROBLEM TO BE SOLVED: To detect a faulty part and the cause of fault on a monitoring panel online. SOLUTION: An I/O device 2 is provided with a CPU 2a and memory 2c, and performs address management of each part unit on a monitoring panel 8 and online abnormality monitoring. Control instruction (e.g. lighting of a display device 4e) from a controller 1 is converted into subordinate data whose station number is a display unit 4 by the device 2 and then is transmitted. The CPU 2a sequentially transmits an abnormality monitoring signal to each unit 3 and 4 while the device 2 is not accessed, and decides the existence of abnormality from the response. A state (on/off) signal of a switch 3e of a switch unit 3 is sent to the device 2 through a transmission device 3b, converted into state data and sent to the controller 1. A CPU 3a performs self-diagnosis of a state of the switch 3e based on the content of memory 3c when its own unit is not accessed, and sends an abnormality detecting signal to the device 2 at the time of uncoincidence.

3. 发明专利

JPH08320711A DRAWING EDITING PROCESSOR 失效
公开(公告)号：JPH08320711A
公开(公告)日：1996-12-03
申请号：JP12470295
申请日：1995-05-24
申请人： HITACHI LTD
发明人： ONISHI HIDEO , SUZUKI OSAMU , KOIWAI JUICHI , KASAI TAKEO
IPC分类号： G06F9/06 , G05B19/05
摘要： PURPOSE: To automate designing and shorten the designing time by automatically generating an interlock as a downstream document from an operation block drawing as an upstream document. CONSTITUTION: This plant design support system generates software 4 for a programmable controller by comparing a mode interlock 11 which shows the operation, protection, etc., of an equipment and an operation block diagram 1 showing the state of the equipment with a data base 3 where a basic logic circuit 2 for the mode interlock is registered. The mode interlock 11 shows the installation place of the COS (operation place switch) of a pump, an automatic/manual discrimination, and the operation and stop of a CS (operation switch). The basic logic circuit 2 extracts only software from the mode interlock 11 and expands it into an interlock ladder diagram. Further, a knowledge process is performed to add and alter an interlock circuit, etc., required for respective circuits.

4. 发明专利

JPH03102404A CONTROLLER 失效
公开(公告)号：JPH03102404A
公开(公告)日：1991-04-26
申请号：JP24001189
申请日：1989-09-18
申请人： HITACHI LTD
发明人： ONISHI HIDEO , KOIWAI JUICHI , ICHIKAWA TETSUO , MIYAMURA HISATO
IPC分类号： G05B15/02
摘要： PURPOSE:To attain the control operations at both high and low speeds by unifying a microcontroller and a sequence controller into one body, separating a memory for instrumentation (DDC) from a memory for electrical control (one- person operator), and performing both the electrical control and the instrument control of a programming device in the same S mode. CONSTITUTION:A programming device 4 for instrumental control of a central computer 1 corrects or changes the set water level and applies the correction/ change to a controller 7 during its operation. Under such conditions, the computer 1 switches an automatic mode to a manual mode via an operating part 3. Then the computer performs a remote loading operation to memory 10 for instrumental control while the controller 7 is working in an electrical control (one-person control) mode. Thus the set water level and a program are changed. As a result, a due operation can be carried on with no stoppage of a lower rank controller (a plant equipment 14). Furthermore the instrumental control (DDC) is attained via an electrical control programming device 11. Thus the highly flexible control is ensured.

5. 发明专利

JPH01177641A DOUBLE SYSTEM COMPUTER DEVICE 失效
公开(公告)号：JPH01177641A
公开(公告)日：1989-07-13
申请号：JP124188
申请日：1988-01-08
申请人： HITACHI LTD
发明人： KOIWAI JUICHI , ONISHI HIDEO
IPC分类号： G06F11/18 , G06F15/16
摘要： PURPOSE:To easily discriminate the action condition of a main system at a salve system by storing a supervisory pattern in an output part, updating it by means of the main system, and supervising the updated supervisory pattern by means of the slave system. CONSTITUTION:A slave system 2 reads the supervisory pattern updated by a main system 1 stored in an output card in the middle of a read action, the supervisory pattern is inspected, and whether the pattern is normally updated or not is checked. At the time of a normal updating, that the action cycle of the main system 1 is completed is decided, and that the action cycle of the main system is completed and the slave system goes into the following action can be confirmed. Consequently, the main system and slave system can be synchronized, and even at the time of waiting, when the updating is abnormal or it is not executed, the slave system 2 decides that the main system 1 is abnormal. Thus, whether a sequence processing is executed or not can be discriminated, and the result is displayed for a supervision to an external part.

6. 发明专利

JP2581611B2 失效
公开(公告)号：JP2581611B2
公开(公告)日：1997-02-12
申请号：JP24908090
申请日：1990-09-19
申请人： HITACHI LTD
发明人： OONISHI HIDEO , KOIWAI JUICHI , OKAMOTO TADASHI , MISHIRO YASUMASA , SHOJI MOTOYUKI
IPC分类号： G05B19/05

7. 发明专利

JPH04114202A CONTROLLER 失效
公开(公告)号：JPH04114202A
公开(公告)日：1992-04-15
申请号：JP23475990
申请日：1990-09-05
申请人： HITACHI LTD
发明人： ONISHI HIDEO , KOIWAI JUICHI , KANEKO TOMONORI , SATO FUJIO , TATE YOSHIO
IPC分类号： G05B9/02 , G05B9/03 , G05B23/02
摘要： PURPOSE:To construct a relayless and cableless system by transmitting signals while switching to a CPU link interface when a common controller breaks down. CONSTITUTION:When the common controller breaks down, signals are transmitted through a CPU link transmission line 5, CPU link interface in a station module 40 of an I/O unit 6 and CPU link interface in the I/O interface of a slave controller to the next slave controller while switching to a CPU link interface 52 in an I/O interface 50 of a slave controller 7. Thus, it is not necessary to fetch the signals of the common part by the slave controller, and the relayless and cableless system can be constructed.

8. 发明专利

JPH02153401A INPUT/OUTPUT DEVICE 失效
公开(公告)号：JPH02153401A
公开(公告)日：1990-06-13
申请号：JP30684388
申请日：1988-12-06
申请人： HITACHI LTD
发明人： ONISHI HIDEO , MORI SHUNJI , YODA MIKIO , KOIWAI JUICHI , OKAMOTO TADASHI
IPC分类号： G05B9/02
摘要： PURPOSE:To prevent erroneous output from being issued even when a bit error occurs in transmission data due to a noise, etc, by making a contact for preventing malfunction only when output is issued from an OR circuit, and validating an output signal from an input/output device for normal operation. CONSTITUTION:The output from a photocoupler 221 drives a relay 321 by the operation of a relay B1 since a contact 72 is made, and a contact 421 is made. Therefore, a load 122 is driven from a power source 121 via a fuse 152, and thereby, a contact 81 is made, and a relay 61 is driven via a rectifier 51, then, a contact 71 is made. In such a way, even when an internal circuit 11 outputs an (input) command erroneously from a photocoupler 211, no output from an internal circuit 12 is issued at that time, and the contact 71 is not made, therefore, the erroneous output is prevented from being issued.

9. 发明专利

JPS6184704A Sequence control circuit 失效
标题翻译：序列控制电路
公开(公告)号：JPS6184704A
公开(公告)日：1986-04-30
申请号：JP20628684
申请日：1984-10-03
申请人： Hitachi Ltd
发明人： ONISHI HIDEO , YAMAMOTO AKIRA , SATO HIROTAKA , KOIWAI JUICHI
IPC分类号： G05B19/05 , G05B19/02
CPC分类号： G05B19/02
摘要： PURPOSE:To handle easily the abnormal processing by cascade-connecting FFs corresponding to the man-hour in a ring shape by means of interposing a delay means between FFs. CONSTITUTION:A sequence control circuit 15 is provided with RS.FFs19 corresponding to the man-hour, and a man-hour checking timer 20 is interposed as a delay means between the RS.FFs, whereby FFs19 are cascade-connected in a ring shape. Thus when an electric power source is turned on, a power-on reset signal P.ON.R is generated. The FF19 in a step 1 is set, while FFs 19 in other steps are reset through an OR gate 21. When jump conditions are not satisfied and only jogging conditions are satisfied, the man-hour checking timer 20 in the posterior stage starts its action after the setting. When the jogging conditions are satisfied after setting the set time, the FF19 in a step 2 is set, while the FF19 in the step 1 is reset. Afterwards the similar action is repeated.
摘要翻译：目的：通过在FF之间插入延迟装置，通过级联连接对应于手工时间的FF形状来处理异常处理。构成：序列控制电路15具有对应于工时的RS.FFs19，并且在RS.FF之间插入有工时检查定时器20作为延迟装置，由此FFs19以环形级联连接。因此，当电源接通时，产生上电复位信号P.ON.R。设置步骤1中的FF19，其他步骤中的FF19通过或门21复位。当不满足跳跃条件并且仅满足慢跑条件时，后级的工时检查定时器20开始其动作设置后。在设定设定时间后，当满足点动条件时，步骤2中的FF19被设定，而步骤1中的FF19被复位。之后重复类似的动作。

10. 发明专利

JP2003122405A PROGRAMMABLE LOGIC CONTROLLER, METHOD FOR CONFIRMING OPERATION OF LADDER SEQUENCE PROGRAM THEREOF, AND DEBUGGING TOOL 审中-公开
公开(公告)号：JP2003122405A
公开(公告)日：2003-04-25
申请号：JP2001316964
申请日：2001-10-15
申请人： HITACHI LTD , HITACHI INF & CONTROL SYST
发明人： AOYAMA NORIHIRO , MASUDA SHIGETO , KOIWAI JUICHI
IPC分类号： G05B19/05 , G05B19/048 , G05B23/02
摘要： PROBLEM TO BE SOLVED: To debug a ladder sequence program even while the subject of control is being controlled. SOLUTION: A programmable logic controller 101 which controls the subject of control by repeatedly running the ladder sequence program 102 at fixed intervals according to signals inputted from the subject of control is provided with a ladder action result transmission program 105 which outputs the result of ladder action to the outside each time one sequence cycle of the ladder sequence program ends. Also a debugging tool 106 is provided with a storage device 111 which receives and stores the results of ladder action externally outputted from the programmable logic controller 101, and a display means 110 for displaying the results of ladder action read from the storage device 111. Thus, detailed data can be monitored off-line even while the sequence is being run.

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