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1. 发明专利

JPS5269246A MICROPROGRAM TEST CONTROL SYSTEM 失效
公开(公告)号：JPS5269246A
公开(公告)日：1977-06-08
申请号：JP14568975
申请日：1975-12-05
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： SUMITANI KAZUO , YAMADA TAKAHIKO , TAKASE JIYUNICHI , NARA SHIGERU , HIRAI FUMIO
IPC分类号： G06F9/26 , G06F9/22
摘要： PURPOSE:To select one of the results of plural tests preferentially by judging plural branch conditions at the same time with a help of one micro-instruction.

2. 发明专利

JPS5384537A DATA CHANNEL UNIT 失效
公开(公告)号：JPS5384537A
公开(公告)日：1978-07-26
申请号：JP16055276
申请日：1976-12-29
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： AWAJI TOSHIO , AMADA HIROYUKI , TAKASE JIYUNICHI , SAKURAI YOSHIO , FURUKAWA KAZUO
IPC分类号： G06F13/12 , G06F3/00
摘要： PURPOSE:To enable the control register to process commonly only with one group to each control unit, by reading out the control register information from the address assigned to the subcontroller of the local memory unit and by setting it to the control register.

3. 发明专利

JPS5356936A TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPS5356936A
公开(公告)日：1978-05-23
申请号：JP13053776
申请日：1976-11-01
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： FURUKAWA KAZUO , YAMADA SHIGEKI , TAKASE JIYUNICHI , TOJIYAMA TAKASHI , YASUI YUTAKA
IPC分类号： G06F9/22 , G06F3/00 , G06F13/12 , H03M7/00
摘要： PURPOSE:To realize the transfer control system whose hardware quantity is reduced by simplifying the circuit performing the processing specific to each transfer mode and the circuit discriminating the transfer starting condition in the transfer control circuit.

4. 发明专利

JPS5344133A DATA CHANNEL DEVICE 失效
公开(公告)号：JPS5344133A
公开(公告)日：1978-04-20
申请号：JP11969476
申请日：1976-10-04
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： SAKURAI YOSHIO , YAMADA TAKAHIKO , TAKASE JIYUNICHI , SHIYOUDA AKIO , AWAJI TOSHIO
IPC分类号： G06F11/30 , G06F3/00 , G06F13/00
摘要： PURPOSE:The method is provided which supervises the response time using the general timer inside a central control unit, so that the execution time of an inputoutput unit starting instruction and the response time of a sub-channel equipment can be supervised without installing the special timer for the time supervision of the instruction.

5. 发明专利

JPS5236440A MICROOPROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS5236440A
公开(公告)日：1977-03-19
申请号：JP11174475
申请日：1975-09-17
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： TAKASE JIYUNICHI , WAKABAYASHI HARUO , YAZAWA KATSUHIKO , FURUKAWA KAZUO , AWAJI TOSHIO
IPC分类号： G06F9/22 , G06F11/22
摘要： PURPOSE:To perform efficient apparatus diagonosis by means of preliminarily memorizing the temporary stoppage instruction information, thereby stopping the micro-motion through micro-cycle being optionally selected in order to read out the on-the-way state of motion.

6. 发明专利

JPS5222841A MICRO PROGRAM CONTROL METHOD 失效
公开(公告)号：JPS5222841A
公开(公告)日：1977-02-21
申请号：JP9856475
申请日：1975-08-15
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： FURUKAWA KAZUO , WAKABAYASHI HARUO , TAKASE JIYUNICHI , ONODERA HIROSHI , UYAMA KATSUO
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38
摘要： PURPOSE:To prepare for next excution of the command during the time of judge/ branch micro command execution.

7. 发明专利

JPS52120641A MICRO PROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS52120641A
公开(公告)日：1977-10-11
申请号：JP3682576
申请日：1976-04-02
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： AWAJI TOSHIO , YAMADA TAKAHIKO , TAKASE JIYUNICHI , OOKAWA KAZUMASA , HIRAI FUMIO
IPC分类号： G06F9/22 , G06F9/26 , G06F9/32
摘要： PURPOSE:To enable easily for the usage of micro instruction with high efficiency and for the control over a plural number of cycles not limited by 1 cycle control, by holding the micro instruction register during a plural number of cycles.

8. 发明专利

JPS5222837A DATA CHANNEL DEVICE 失效
公开(公告)号：JPS5222837A
公开(公告)日：1977-02-21
申请号：JP9856875
申请日：1975-08-15
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： HIRAI FUMIO , YAMADA TAKAHIKO , TAKASE JIYUNICHI , ONODERA HIROSHI , UYAMA KATSUO
IPC分类号： G06F13/12 , G06F3/00
摘要： PURPOSE:In the data channel device under micro program control system, it is made possible to reduce the program steps required in judging transfer word status.

9. 发明专利

JPS6115235A Central processor 失效
标题翻译：中央处理器
公开(公告)号：JPS6115235A
公开(公告)日：1986-01-23
申请号：JP13408884
申请日：1984-06-30
申请人： Oki Electric Ind Co Ltd
发明人： HIRUKO TAKAHIKO , WATANABE TAKASHI , TAKASE JIYUNICHI
IPC分类号： G06F9/38
摘要： PURPOSE: To perform the comparative calculation of addresses without using any special comparator by using an idle state of an arithmetic logical operatioin circuit to compare the address scales and detecting a state where a prefetch instruction string is invalidated.
CONSTITUTION: A store start address is set to a RAM9 together with the store byte number set to a BC10 respectively, and a memory store action is started. Then the contents of the RAM9 and the store byte number are shunted to an SMAR11 and an SBC12 respectively. Therefore the write data byte position is invalidated if it is positioned in a prefetched instruction area enclosed by (PC) and (IAR) as long as a prefetch instruction train is invalid. Thus (SMAR)+ (SBC)>(PC) and (SMAR)
摘要翻译：目的：通过使用算术逻辑运算电路的空闲状态比较地址比例和检测预取指令字符串无效的状态，不使用任何特殊比较器来执行地址的比较计算。构成：将存储起始地址设置为RAM9，并将存储字节数字分别设置为BC10，并开始存储器存储动作。然后将RAM9的内容和存储字节数分别分别分配给SMAR11和SBC12。因此，只要预取指令序列无效，写入数据字节位置就位于由（PC）和（IAR）包围的预取指令区域中。因此满足（SMAR）+（SBC）>（PC）和（SMAR）<（IAR），其中（PC）<=（IAR）被满足。为了检查所述等式的条件，与存储器存储动作并行地进行比较运算。当满足所述等式的条件时，IBR14内的指令序列无效。然后将（PC）传送到IAR13，再次开始指令的预取动作，并读取改变的指令字符串。

10. 发明专利

JPS613252A ADDRESS CONVERSION SYSTEM 失效
公开(公告)号：JPS613252A
公开(公告)日：1986-01-09
申请号：JP12368284
申请日：1984-06-18
申请人： OKI ELECTRIC IND CO LTD
发明人： NOJIMA HIROMI , TAKASE JIYUNICHI
IPC分类号： G06F12/02 , G06F12/06
摘要： PURPOSE:To reduce the quantity of hardware while maintaining processing ability by obtaining address conversion information from an address conversion list unless there is no effective address conversion information in the address conversion table. CONSTITUTION:The BANK in an input/output main storage address is used to refer to ATB provided to an address converter. The low-order 10 bits of RPA are compared with the PA of the main input/output main storage address and when they do not coincide with each other, it is decided that the entry is ineffective and an address conversion list pointer ATLP is referred to. The sum of the contents of the ATLP and the PA of the input/output main storage address is used as a system main storage address to refer to the ATL, thereby updating the contents of the ATB corresponding to the BANK while deciding on the RPA of the system main storage address. The RPA is combined with a part D of the input/output main storage address to perform address conversion and used as the system main storage address to perform data transfer.

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