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1. 发明专利

JPS5844546A TRAP SYSTEM 失效
公开(公告)号：JPS5844546A
公开(公告)日：1983-03-15
申请号：JP14101081
申请日：1981-09-09
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , JAPAN STORAGE BATTERY CO LTD , FUJITSU LTD
发明人： TAKI YOSHIHARU , OKADA KATSUYUKI , OOTA YOSHIHISA , SAKATA HIRONOBU , URUSHIBARA TETSUO
IPC分类号： G06F11/28 , G06F11/36
摘要： PURPOSE:To eliminate an ineffective interruption of trap, by applying an interruption only in case the contents of a storage device or a register are changed due to a defect of a program. CONSTITUTION:When a memory changing trap is carried out, the address of a storage device MEM with which a program defect is expected is previously set to a trap address register 11. At the same time, the normal data corresponding to the address shown by the register 11 is set to a trap data register 12. The bit position 2 of a trap control register 10 is set at 1. Then the address in a memory address register 13 which is replaced by a coincidence circuit 20 with each writing to the MEM is collated with the address in the register 11. In case the coincidence is detected between both addresses and at the same time the discordance is detected between the writing data in a memory data register 14 corresponding to the relevant address and the normal data in the register 12, a defect of the program is decided. Thus an interruption is applied to an interrupting circuit via an AND circuit 40 and an OR circuit 50.

2. 发明专利

JPS5840665A BIT INSERTION SYSTEM 失效
公开(公告)号：JPS5840665A
公开(公告)日：1983-03-09
申请号：JP13946381
申请日：1981-09-04
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： TOJIYAMA TAKASHI , OKADA KATSUYUKI , UBUKATA NAOYA , MASUDA TAKESHI , URUSHIBARA TETSUO
IPC分类号： G06F7/00 , G06F7/74 , G06F7/76
摘要： PURPOSE:To simultaneously transfer an optional bit train data to other field, by supplying a shifting quantity and a suppressing quantity to 2 shifting and suppressing circuits, respectively, and shifting the logic of these operation results. CONSTITUTION:The first data and the second data which have been read out from a main memory MM are inputted to the first shifting circuit SFTO and the second shifting circuit SFT1, respectively. Subsequently, a data inputted to the circuit SFT0 is shifted in accordance with information of a shifting quantity supplied from a register SFNO, is inputted to a suppressing circuit SUPO, also is suppressed in accordance with information of a suppressing quantity from a register SPNO, and is inputted to a lgical OR circuit OR. On the other hand, a data inputted to the circuit SFT1 is also inputted to the circuit OR in the same way. Subsequently, when a result of operation of the circuit OR is shifted by a register SFT2, an optional bit train data of a data in the main memory MM can be transferred to other different field at the same time.

3. 发明专利

JPH0877082A TESTING METHOD FOR INFORMATION TRANSFER CONTROL PART 失效
公开(公告)号：JPH0877082A
公开(公告)日：1996-03-22
申请号：JP20834694
申请日：1994-09-01
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD
发明人： IDETANI SEIJI , KOMACHIYA TADAYOSHI , OKADA KATSUYUKI , TAWARA TAMOTSU
IPC分类号： G06F11/22 , G06F13/00
摘要： PURPOSE: To eliminate the need for management data by 10 devices that a CPU device holds and to facilitate the demarcation of a faulty device by equipping a function board, connected to the serial bus of a system, with a data transmitting and receiving/collating circuit which tests the normalcy of its bus interface control part. CONSTITUTION: Plural function boards 2 equipped with bus interface control parts 3 respectively are connected to the serial bus 1, and each function board 2 is equipped with the data transmitting and receiving/collating circuit 6 which transmits information to the serial bus 1 and receives the information from the serial bus 1. When the serial bus 1 is not in use, information addressed to its function board 2 is sent to the serial bus 1 by using the data transmitting and receiving/collating circuit 6 and the information is received from the serial bus 1, thereby testing the normalcy of the bus interface control part 3.

4. 发明专利

JPH10301895A BUS EXTENSION DEVICE 失效
公开(公告)号：JPH10301895A
公开(公告)日：1998-11-13
申请号：JP11251197
申请日：1997-04-30
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAZAKI KOICHI , TAWARA TAMOTSU , MURAKAMI HIDEYUKI , OKADA KATSUYUKI , AOKI MICHIHIRO , HOSAKA TOKUO
IPC分类号： G06F13/36
摘要： PROBLEM TO BE SOLVED: To provide the bus extension device which can convert the width of data according to the data widths of two parallel buses which have different widths and transfer the data between the buses. SOLUTION: Parallel data DB0 to DB63 from a data signal line 41 of an extension bus 40 are held by FF22 and supplied to a selector 23. The selector 23 selects the low-order bits DB0 to DB31 and high-order bits DB32 to DB63 alternately according to a clock signal CKA and outputs them to a buffer 24. A transfer control part 25 performs ON/OFF control over the output from the buffer 24 to a system bus 30 according to the address and data length of the transfer data. Parallel data DA0 to DA31 from a data signal line 31 of the system bus 30, on the other hand, are held by FFs 27a and 27b alternately and outputted to buffers 28a and 28b. A transfer control part 29 performs ON/ OFF control over the output from the buffers 28a and 28b to the extension bus 40 according to the address and data length of the transfer data.

5. 发明专利

JPS5899870A INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPS5899870A
公开(公告)日：1983-06-14
申请号：JP19766781
申请日：1981-12-10
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： OOTA YOSHIHISA , OKADA KATSUYUKI
IPC分类号： G06F15/17 , G06F13/364 , G06F13/40
摘要： PURPOSE:To elevate throughput of a bus, and also to reduce an occupied time of the bus, by taking a time division transfer system as an interface of a common bus, and also providing a temporary storage function on a bus adaptor. CONSTITUTION:In case when a CPU 01-1 reads out a data from a common memory 5, the CPU 01-1 sends out a separate bus using request to a separate bus arbiter 26 of a bus adaptor 1-6, and sends out a synchronizing signal and an address information toa separate bus 1-5. An information transfer destination detecting circuit 12 of the adaptor 1-6 receives these signal and information, and starts a separate bus interface controlling circuit 14 and a common bus interface controlling circuit 15. The circuit 14 sends out a bus adaptor response signal to the bus 1-5 unless the adaptor 1-6 is in the course of a transfer operation between buses. When this signal is received, the CPU 01-1 enters into a waiting operation of a synchronizing signal for response information. On the other hand, the adaptor 1-6 sends out a using request signal of a common bus, to the bus arbiter by the circuit 15. The arbiter 4 sends back an approval signal in accordance with the priority order.

6. 发明专利

JPH10312354A INTERRUPTION PROCESSING SYSTEM 失效
公开(公告)号：JPH10312354A
公开(公告)日：1998-11-24
申请号：JP12052797
申请日：1997-05-12
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAWARA TAMOTSU , YAMAZAKI KOICHI , MURAKAMI HIDEYUKI , OKADA KATSUYUKI , AOKI MICHIHIRO , IDETANI SEIJI
IPC分类号： G06F13/24 , G06F9/46 , G06F9/48
摘要： PROBLEM TO BE SOLVED: To standardize software processing and to shorten an interruption processing time by eliminating contradiction between the processing by software and the state of hardware. SOLUTION: When an interruption generating units (IU) 41 or 42 initiate an interruption, an interruption gathering means (INTU) 40 receives the interruption, sets a flag 51-1 corresponding to the IU 41 or 42 having initiated the interruption, and interrupts a central processing unit(MPU) 60 when the flag 51-2 corresponding to the IU 42 is not set or does not interrupt the MPU 60 when the flag 51-2 is set. Further, when an instruction for clearing the flag 51-1 is executed by the MPU 60, the INTU 50 interrupts the MPU 60 if there is the set flag 51-2 present even after the clearing.

7. 发明专利

JPH08195774A RELAY TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPH08195774A
公开(公告)日：1996-07-30
申请号：JP371695
申请日：1995-01-13
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD
发明人： IDETANI SEIJI , KOMACHIYA TADAYOSHI , OKADA KATSUYUKI , TAWARA TAMOTSU , WADA NOBORU
IPC分类号： G06F3/00 , H04L13/08 , H04L29/10
摘要： PURPOSE: To improve maintenance of a system provided with a repeater by allowing the repeater relaying information to suppress reception of information from another equipment till the information of the repeater is finished for transmission. CONSTITUTION: A repeater 4 at a basic bus side uses a power detection/notice control section 12a to detect application of power at insertion of an alive line or application of power to set a reception suppression flag of a control register 13a to 1 and sends its own alive line insert notice to an information processing unit 6. When the insertion of the alive line is finished, a reception suppression flag of the register 13a is cleared to 0 thereby releasing suppression control of an information input from a relay signal line 3 by a relay transfer control section 11a. When information is received from the signal line 3, the control section 11a receives the information from the signal line 3 and sends the information to a basic serial bus 1. That is, the repeaters 4, 5 suppress reception of information from other equipments till the self information of the repeaters 4, 5 is finished for transmission.

8. 发明专利

JPH11175458A DEVICE STATE COMMUNICATION PROCESSING METHOD 失效
公开(公告)号：JPH11175458A
公开(公告)日：1999-07-02
申请号：JP34143497
申请日：1997-12-11
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD
发明人： OKADA KATSUYUKI , IDETANI SEIJI , MASUDA ETSUO , SATO KIYOMI , TAWARA TAMOTSU , YAMAZAKI KOICHI
IPC分类号： G06F13/14
摘要： PROBLEM TO BE SOLVED: To provide a device state communication processing method for unnecessitating a preserving operation procedure under the consideration of the mounting state of a CPU and the hot-like insertion procedure of a device, for making it unnecessary to consider any insertion procedure even at the time of hot-line inserting plural devices, and four preventing the loss of device state information to be transferred. SOLUTION: Plural devices (CPU 2, devices 3-1 to 3-n) having information transmitting and receiving means (data transmission and reception control circuits 7-0 to 7-n) are connected by an information transferring means (bus 1 for device state communication). Any one device (3-1 to 3-n) transmits its own device state information (hot-line insertion information), and the CPU 2 receives the state information. At the time of normally receiving the state information, the CPU 23 returns information indicating that the state information is normally received to the devices (3-1 to 3-n) being the origin of transmission of the state information, and the devices (3-1 to 3-n) being the origin of transmission of the state information repeat the transmission of the state information until receiving the information indicating the normal reception of the state information. This system is provided with a bus interface control part 4.

9. 发明专利

JPH1174856A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPH1174856A
公开(公告)日：1999-03-16
申请号：JP24775497
申请日：1997-08-28
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SATO KIYOMI , TAWARA TAMOTSU , MURAKAMI HIDEYUKI , AOKI MICHIHIRO , OKADA KATSUYUKI , KATAOKA SHINSUKE
IPC分类号： H04J3/00 , H04L29/08
摘要： PROBLEM TO BE SOLVED: To reduce the number of signal lines connecting data transferring devices, and to reduce package space and cost by multiplexing a data signal and a state control signal into serial data, and transferring it, and demultiplexing the serial data into the state control signal and the data signal by using the state control signal transferred separately from the serial data, and reproducing. SOLUTION: A multiplex converting circuit 8 of a data transferring device 1 at a transmitter side converts a control signal from a synchronizing circuit 6 and a data signal from a transmission register 7 into one bit serial data, and outputs it. A demultiplex converting circuit 11 of a data transferring device 2 at a receiver side demultiplexes the serial data inputted from a data line 3 into the first half and the second half, and distributes the data to a control register 12 and a reception register 13. The serial data are converted into parallel data, and the control signal and the data signal are restored. This data transfer control is operated through a CLK signal line 4 and an SYNC signal line 5 being a transfer control line 10.

10. 发明专利

JPH10303942A BUS CONNECTING DEVICE 失效
公开(公告)号：JPH10303942A
公开(公告)日：1998-11-13
申请号：JP11251397
申请日：1997-04-30
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAWARA TAMOTSU , NAKANO NAOKI , IWAMURA KEIJI , AOKI MICHIHIRO , OKADA KATSUYUKI , KATAOKA SHINSUKE
IPC分类号： G06F1/24 , G06F13/38 , H04L12/40
摘要： PROBLEM TO BE SOLVED: To set an insertion order of a function block as optional, to reduce the number of signal lines of a bus and to make a device compact. SOLUTION: In the case that a function block 40 is inserted into a bus at a state that a function block 50 is mounted, when power supply voltage of the function block 40 is determined, a bus clock CK is started to be supplied from a clock supplying circuit 41. A fact that clock interruption lasts until the clock CK is normally supplied by the circuit 41 is detected and a clock interruption reset signal S51 is turned on by a clock interruption detecting circuit 51. The signal S51 is turned off after a fixed period from the clock CK is judged to be normally inputted by the circuit 51. Consequently, an interface circuit 54 is normally reset by a fact that an internal reset signal is turned on while the clock CK is supplied and communication with a serial bus 30 is normally performed when the signal S52 is turned off.

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