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1. 发明专利

JPS5840665A BIT INSERTION SYSTEM 失效
公开(公告)号：JPS5840665A
公开(公告)日：1983-03-09
申请号：JP13946381
申请日：1981-09-04
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： TOJIYAMA TAKASHI , OKADA KATSUYUKI , UBUKATA NAOYA , MASUDA TAKESHI , URUSHIBARA TETSUO
IPC分类号： G06F7/00 , G06F7/74 , G06F7/76
摘要： PURPOSE:To simultaneously transfer an optional bit train data to other field, by supplying a shifting quantity and a suppressing quantity to 2 shifting and suppressing circuits, respectively, and shifting the logic of these operation results. CONSTITUTION:The first data and the second data which have been read out from a main memory MM are inputted to the first shifting circuit SFTO and the second shifting circuit SFT1, respectively. Subsequently, a data inputted to the circuit SFT0 is shifted in accordance with information of a shifting quantity supplied from a register SFNO, is inputted to a suppressing circuit SUPO, also is suppressed in accordance with information of a suppressing quantity from a register SPNO, and is inputted to a lgical OR circuit OR. On the other hand, a data inputted to the circuit SFT1 is also inputted to the circuit OR in the same way. Subsequently, when a result of operation of the circuit OR is shifted by a register SFT2, an optional bit train data of a data in the main memory MM can be transferred to other different field at the same time.

2. 发明专利

JPS55100798A CONTROL SYSTEM OF CHANNEL MEMORY UNIT 失效
公开(公告)号：JPS55100798A
公开(公告)日：1980-07-31
申请号：JP826079
申请日：1979-01-29
申请人： OKI ELECTRIC IND CO LTD
发明人： FURUICHI SHIYOUZOU , MIYAHARA NOBUYUKI , UBUKATA NAOYA , KURACHI YOSHIAKI
IPC分类号： H04M3/22 , H04Q3/545 , H04Q11/04
摘要： PURPOSE:To make it possible to read and write freely the contents of a channel memory unit by adding one control bit to each word in the channel control unit and then by controlling them by CPU. CONSTITUTION:When the contents of channel memory unit TSPM are rewritten by an instruction from CPU, gate circuits 10 and 13 are closed and circuit 11 and 14 are opened to write a combination of an information l bit and one control bit at an assigned address from CPU. The control bit at this time is set to ''0'' for write inhibition and its address is denoted by X. Write pulse generating circuit 17 is enable to generate a write pulse all the time on arrival of an instruction from CPU. Even if write operation would be done at address X by the indication of an address control circuit when normal switching operation is put into effect again, address X is read prior to the write operation and the control bit is held by latch circuit 16 for inhibiting the write operation. As a result, the contents of address X are unchangeable and even if address would be read by CPU, the previously-written contents never change. To return address X to normal operation, the write inhibition bit is only reset by the instruction of CPU.

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