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1. 发明专利

JPS60174963A ELECTRONIC PACKAGE TESTING CIRCUIT 失效
公开(公告)号：JPS60174963A
公开(公告)日：1985-09-09
申请号：JP3027084
申请日：1984-02-22
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： TAKI YOSHIHARU , WAKIMURA YOSHIAKI , SAKURAI YOSHIO , URUSHIBARA TETSUO
IPC分类号： G01R31/28 , G01R31/316 , H01L21/66 , H01L21/822 , H01L27/04
摘要： PURPOSE:To enable an operation test of a logic circuit by arranging an input terminal to be used only for operation test on an LSI circuit and a circuit which provides an output from the input terminal with a higher impedance of all of the output terminals and bi-directional terminals of the integrated circuit to electrically cut the logic circuit off the LSI circuit. CONSTITUTION:Output terminals 7 and 8 of an integrated circuit 9 are connected to perform an operation test of a combination logic circuit 14 having an input terminal 15 and to be more specific, the operation of an inverter 17, an AND circuit 18 and a NAND circuit 19 is checked. So, the outputs of AND circuits 1 and 2 go to the L level by setting the input terminal 6 of the integrated circuit 9 at the H level. Therefore, as tristate gates 3 and 4 are turned to a high impedance, the output terminal 7 and the bi-directional output terminal 8 also give a high impedance. This electrically cuts the combination logic circuit 14 in an electronic package off the integrated circuit 9 thereby facilitating the operation test of the logic circuit.

2. 发明专利

JPS60136835A GUARD PROCESSING METHOD OF IMPORTANT SIGNAL 失效
公开(公告)号：JPS60136835A
公开(公告)日：1985-07-20
申请号：JP24405783
申请日：1983-12-26
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： TAKI YOSHIHARU , KITANO HIROSHI , ABE HIROAKI
IPC分类号： G06F9/46 , G06F9/48 , G06F11/00 , G06F11/07
摘要： PURPOSE:To prevent an important signal from malfunction even if softwave runs away by executing respective program tasks independently and sending output information in accordance with respective program tasks. CONSTITUTION:A task schedular 7 makes the program tasks 5, 6 execute alternately at 100ms period by a time interrupting method or the like. If an output signal 3 is set up to ''1'' and sent in error when a processor 1 executes malfunction due to noise or the like, a program runs away, the program task 5 executes a step for setting up the outut signal 3 to ''1'', and an input signal 2 is ''0'', the execution of the program is returned to the task schedular 7, so that the program task 6 is executed from its head and an output signal 4 is not turned to ''1''. Thus both the output signals 3, 4 are scarecely set up to ''1'' simultaneously.

3. 发明专利

JPS5559566A MAINTENANCE PANEL CONTROL SYSTEM 失效
公开(公告)号：JPS5559566A
公开(公告)日：1980-05-06
申请号：JP13260278
申请日：1978-10-30
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： YASUDA KENICHI , ISHITSUKI TAKEO , OOKAWA KAZUMASA , TAKI YOSHIHARU , SUZUKI HITOSHI
IPC分类号： G06F11/22 , G06F11/32
摘要： PURPOSE:To miniaturize the device by carrying out the microprogram control with the run/stop mode of the central control unit used as the branch condition of the microprogram. CONSTITUTION:The run/stop test is given at the head of the execution microprogram with every execution of each order at central control unit CC. The contents test of flip-flop STOPF/F is carried out at conditions test circuit TEST to decide the address of microprogram generation circuit SEQ. When unit CC is in the run mode, the control is given to input/output device IOC including maintenance panel device MP. While in case CC is in the stop mode, device MP is controlled directly via the microprogram and through the same control as the input/output order of the program. Thus the control for the maintenance and test purposes is possible via the program at the operation time.

4. 发明专利

JPS5525153A INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPS5525153A
公开(公告)日：1980-02-22
申请号：JP9817278
申请日：1978-08-14
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： TAKI YOSHIHARU , WAKABAYASHI HARUO , MORISAWA TADAKAZU , USHIKI TATSUO , SEO TOMIHIDE , TACHIKA SHINJI
IPC分类号： G06F13/12 , G06F3/00 , G06F12/10 , G06F13/00
摘要： PURPOSE:To improve the function of a system by increasing the versatility of software by providing a page register in a data channel unit, by inputting and outputting the address information of this register by input and output command words, and by performing page transfer on each channel actuation. CONSTITUTION:An address space which can be assigned by a single instruction is regarded as a unit page and a plural number of this pages are stored in memory 1. To attain access to memory 1 from data channel unit 2, the output of page register 5 is used which is provided in data channel unit 2 and is stored with page address information. Then, this page register 5 is set by input and output operation command words and to this page register 5, page address transmitting gate 6 which sends page address in memory access and fixed-page assignment jumper circuit 8 are connected so as to send addresses to memory 1 and also to transfer jumper setting discrimination signal 9 to the control circuit.

5. 发明专利

JPS58112126A INCORPORATING SYSTEM OF CHANNEL WORD MEMORY 失效
公开(公告)号：JPS58112126A
公开(公告)日：1983-07-04
申请号：JP21567181
申请日：1981-12-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： YASUI YUTAKA , ITOU YOSHITAKA , KAJIZUKA SHIYOUJI , OOKAWA KAZUMASA , TAKI YOSHIHARU
IPC分类号： G06F13/12
摘要： PURPOSE:To minimize a data channel, by deleting an unnecessarily excessive storage capacity out of a channel word memory incorporated into a data channel device and setting the channel word memory to a scale that can store the minimum necessary number of channel words for a practical use. CONSTITUTION:A data channel device 3 collates the received device address with a registered device address through a device address registering/collating part 6. If coincidence is obtained with either one of registered device addresses, the channel word CHWJ corresponding to the coincident registered address within an incorporated channel word memory 5 is read out of a control part 7 and fed to an arithmetic part 8 as well as to be stored in a register. The information stored in the register is replaced with another information as the input/output operation proceeds. Then this stored information is stored at a prescribed region of the memory 5 as soon as a series of control operations is over with a data channel device 30 or 31.

6. 发明专利

JPS60134367A COMMUNICATION SYSTEM BETWEEN PLURAL PROCESSORS 失效
公开(公告)号：JPS60134367A
公开(公告)日：1985-07-17
申请号：JP23977083
申请日：1983-12-21
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKI YOSHIHARU , KURAYA ETSUJI
IPC分类号： G06F15/16 , G06F15/163 , G06F15/177
摘要： PURPOSE:To decrease invalid communication between processors by transmitting communication order re-request order for the processor which transmits the communication order to the self device. CONSTITUTION:Communication orders from order processors are received, and it is decided that they are the communication orders for the self device by a matching circuit 12. Then, the transmitter number is duted by a dute circuit 14, and an AND circuit 17 which corresponds to the transmission processor is conducted by the output of the dute circuit 14 and a busy tone 16. The orders are stored in a flip-flop 18. When a main control part 15 terminates the processing of the communication orders in processing, the output of an OR circuit 19 is tested, when it turns on, an output 20 is tested, and the number of the transmitter is discriminated. Then, an operation part 21 is operated, a bus format is formed, and the communication order re-request orders for communication order retransmission are transmitted.

7. 发明专利

JPS5844546A TRAP SYSTEM 失效
公开(公告)号：JPS5844546A
公开(公告)日：1983-03-15
申请号：JP14101081
申请日：1981-09-09
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , JAPAN STORAGE BATTERY CO LTD , FUJITSU LTD
发明人： TAKI YOSHIHARU , OKADA KATSUYUKI , OOTA YOSHIHISA , SAKATA HIRONOBU , URUSHIBARA TETSUO
IPC分类号： G06F11/28 , G06F11/36
摘要： PURPOSE:To eliminate an ineffective interruption of trap, by applying an interruption only in case the contents of a storage device or a register are changed due to a defect of a program. CONSTITUTION:When a memory changing trap is carried out, the address of a storage device MEM with which a program defect is expected is previously set to a trap address register 11. At the same time, the normal data corresponding to the address shown by the register 11 is set to a trap data register 12. The bit position 2 of a trap control register 10 is set at 1. Then the address in a memory address register 13 which is replaced by a coincidence circuit 20 with each writing to the MEM is collated with the address in the register 11. In case the coincidence is detected between both addresses and at the same time the discordance is detected between the writing data in a memory data register 14 corresponding to the relevant address and the normal data in the register 12, a defect of the program is decided. Thus an interruption is applied to an interrupting circuit via an AND circuit 40 and an OR circuit 50.

8. 发明专利

JP2000244435A DATA COMMUNICATION EQUIPMENT 失效
公开(公告)号：JP2000244435A
公开(公告)日：2000-09-08
申请号：JP4092399
申请日：1999-02-19
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKI YOSHIHARU , SATO HIROSHI , IRIE KAZUNARI
IPC分类号： H04J3/00 , H04J3/04 , H04L12/879 , H04L12/951 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To reduce a processing load required for transmission control when the number of the channels of a multiplex line becomes large by connecting a next transmission descriptor whose channel number is similar to a transmission descriptor whose transmission is completed to the descriptor string of different channel numbers. SOLUTION: Transmission is executed based on the descriptor string of different channel numbers. The next transmission descriptor whose channel number is similar to a transmission descriptor whose transmission is completed is connected to the descriptor string of the different channel number. In data communication equipment 100, a transmission completion processing part 122 reads the transmission descriptor receiving a transmission completion report. The descriptor string shown by the same channel NEXT descriptor number of the transmission descriptor is referred to. The transmission descriptor next to the transmission descriptor whose transmission processing is completed is connected to the descriptor string show by the different channel NEXT descriptor number.

9. 发明专利

JPS5816326A DATA CHANNEL CONTROLLING SYSTEM 失效
公开(公告)号：JPS5816326A
公开(公告)日：1983-01-31
申请号：JP9671581
申请日：1981-06-24
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKI YOSHIHARU
IPC分类号： G06F13/12
摘要： PURPOSE:To obtain an economical data channel device, by providing the memories that store the channel words using an input/output device in a time division way and in the number equal to the input/output devices which are actually used at one time. CONSTITUTION:A data channel device receives an input/output instruction from a CPU and then a control part 12 puts the data of IOA on a writing bus 13. This data is set to an IOA buffer 4. Then an idle bit position of an idle bit register 1 of a channel word CHW is detected by a detecting circuit 3, and the address of a CHW memory 9 is written into a CHW address memory 6. The contents of the memory 6 are read by a CHWA memory reading signal 8 to know the address of the memory 9, and 1 is written to the bit of the register 1 corresponding to the address of the memory 9. After this, the corresponding IOA is set to the buffer 4 with each reception of the data and then read and written out/into the memory 9. The transfer is controlled between an input/output device and a storage device by the contents of the memory 9. Accordingly it is not necessary to have the CHW memories equivalent to the maximum number of the input/output devices.

10. 发明专利

JPS59229923A LOGICAL CIRCUIT FOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS59229923A
公开(公告)日：1984-12-24
申请号：JP10414483
申请日：1983-06-13
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKI YOSHIHARU , MIKI SHIYUUJI , WAKIMURA YOSHIAKI
IPC分类号： H03K19/003
摘要： PURPOSE:To stabilize the simultaneous switching of output terminal signals of a large-scale IC by obtaining a logic between the signal supplied from an input terminal of an IC and the switch control signal of the output terminal signal. CONSTITUTION:A clock signal C1 is supplied in common to latch FF1 and 2, and data signals D1 and D2 are supplied to terminals D of the FF1 and 2 respectively. The gate signals G1 and G2 of tri-state gate groups 3 and 4 are delivered from the FF1 and 2 to perform the simultaneous switching of output terminal signals 5 and 6 of an IC. An input terminal 12 is provided to this IC, and the timing signal D3 supplied from the terminal 12 and the output signal Q of the FF1 are supplied to an AND circuit 13. The signals D1 and D2 are supplied at a time, and the FF1 and 2 deliver them at a time. However an AND 13 is obtained between the output Q of the FF1 and the signal D3, and the signal G1 is delivered. Therefore a time difference T is produced between the signals G1 and G2, and no simultaneous switching of signals is carried out between output terminal groups 5 and 6. Thus the simultaneous switching frequency is reduced to ensure a stable switching operation.

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