专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS6268339A TOKEN CONTROL SYSTEM 失效
公开(公告)号：JPS6268339A
公开(公告)日：1987-03-28
申请号：JP20654485
申请日：1985-09-20
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP , FUJITSU LTD
发明人： TAKIYASU YOSHIHIRO , TAKAI ATSUSHI , WADA KENICHI , HOSHIKO TAKAYUKI , IBORI SHOICHI , KAMINOMURA HITOSHI
IPC分类号： H04L12/42
摘要： PURPOSE:To obtain a token control system not causing a fault attended with the missing of a reply frame by sending a token frame after reply frame sending independently of the reply region after each node sends the information frame sent from its own node and addressed to its own node. CONSTITUTION:When the information frame sent attended with the acquisition of transmission right is a frame addressed to its own node, a logic layer decides a frame addressed and sent to its own node ahead the preparation of transmission, functions the sequence control in advance to set the procedure in the order of the transmission instruction of the reply frame and the transmission instruction of a token frame. Then a signal G inhibits the 1st token frame transmission control and follows the token frame transmission instruction from the logic link layer given through a signal line F and then a signal line C. The logic link layer applies the transmission instruction of the reply frame after the reception of the information frame addressed and sent to/from its own node to apply the token frame transmission instruction.

2. 发明专利

JPS59229925A LOGICAL CIRCUIT 失效
公开(公告)号：JPS59229925A
公开(公告)日：1984-12-24
申请号：JP10413883
申请日：1983-06-13
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKAI ATSUSHI , YUMOTO OSAMU , HIRAYAMA MASAHIRO , IDA MASAO
IPC分类号： H03K19/0952 , H03K19/094 , H03K19/0944
摘要： PURPOSE:To obtain a logical circuit which can attain a high yield, low power consumption and highly integrated structure by using an FET having the threshold voltage of larger absolute value than the logical amplitude of output as a current/voltage conversion resistance of a current switch type logical circuit. CONSTITUTION:A current/voltage conversion element is formed with MOSFET4' and 5' having gates and sources connected to each other for a current switch type logical CML circuit consisting of a normally-on type FET. For instance, an input 100 is defined as the reference voltage Vref, and FET2 and 3 are turned on and off respectively if an input 101 is higher than the voltage Vref. Thus outputs 200 and 201 are set at 1 and 0 respectively. When the output 101 is lower than the Vref, the outputs 201 and 200 are set at 1 and 0 respectively. In this case, the absolute value of the threshold voltage of the FET4' and 5' is set larger than a logical amplitude respectively and used in a non-saturated area. Thus the current of a constant current source 1 can be reduced, and the constant current has virtually no change despite the variance of the FET2 and 3. This attains the low power consumption and a high yield.

3. 发明专利

JP2001005746A FILE TRANSFER SYSTEM 失效
公开(公告)号：JP2001005746A
公开(公告)日：2001-01-12
申请号：JP17339499
申请日：1999-06-18
申请人： NIPPON TELEGRAPH & TELEPHONE , NTT COMM KK
发明人： OGIWARA TOSHIHIKO , YAMASHITA TOYOICHIRO , TAKAI ATSUSHI , ISHII SHIGERU , SUDO SHINOBU , HASEBE JUN
IPC分类号： G09C1/00 , G06F13/00 , H04L9/08 , H04L12/54 , H04L12/58
摘要： PROBLEM TO BE SOLVED: To secure the convenience of a user and to permit use like a batch processing for transferring a large-amount file by using HTTP (hypertext trans fer protocol) which is safe against the tapping and forgery of a file and imper sonation as a sender or receiver and flexibly allow passage through a fire wall while an electronic file is sent and received through an IP(Internet protocol) network such as the Internet. SOLUTION: This file transfer system transfers an electronic file 006 from a transmitting client 003 to a receiving client 004 by a network 002 through a transfer server 001 and performs the transfer between the clients by using a control file wherein information regarding the transferred electronic file 006 is described. In this control file, one or more pieces of information on the transfer destination of the file are described and information regarding the transfer procedure of the file with the transfer server and security control is described.

4. 发明专利

JPH11296583A CONTENTS CHARGING METHOD, ITS SYSTEM, ALTERNATIVE SERVER AND MEDIUM FOR STORING CONTENTS CHARGING PROGRAM 失效
公开(公告)号：JPH11296583A
公开(公告)日：1999-10-29
申请号：JP9737998
申请日：1998-04-09
申请人： NIPPON TELEGRAPH & TELEPHONE , NTT PC COMMUNICATIONS KK
发明人： TAKAI ATSUSHI , OGIWARA TAKESHI , MORITA YUICHI , OSHIMA KAKUMORI , KATAYAMA HARUKI , UEHARA TAKAYUKI , MURAKAMI MAMORU , HARA RYUICHI
IPC分类号： B65G61/00 , G06F13/00 , G06F15/00 , G06F21/00 , G06F21/10 , G06F21/31 , G06Q20/00 , G06Q20/40 , G06Q20/42 , G06Q30/04 , G06Q30/06 , G06Q40/00 , G06Q40/02 , G06Q50/00 , G06F17/60
摘要： PROBLEM TO BE SOLVED: To allow even a user of plural different providers to purchase merchandise by providing an alternative server for alternatively executing the requests of identification and charging of the user. SOLUTION: An alternative server extracts information on a provider to be a requesting destination of identification processing from an identification request obtained from a store WWW server and issues the identification request to a provider concerned in information on the provider (S4), obtains the identifying result from the provider (S5), returns it to the shop WWW server (S6), obtains a charging request from the shop WWW server (S7), extracts information on the provider to be the requesting destination of the charging request from the obtained charging request so as to issue the charging request to the provider concerned (S8), and obtains a charging result from the provider (S9) to return it to the shop WWW server (S10). The shop WWW server provides merchandise to a WWW browser based on the charging result (S11).

5. 发明专利

JPH08241228A DATA BASE DEVICE AND DATA RETRIEVAL METHOD 失效
公开(公告)号：JPH08241228A
公开(公告)日：1996-09-17
申请号：JP4578395
申请日：1995-03-06
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： YONEZAWA SHINJI , NAKAI TOSHIO , DAIKUMACHI KAZUHIRO , HAYASHI TAKEO , IMAMURA YOSHIHARU , TAKAI ATSUSHI , TSUJI TAKASHI
IPC分类号： G06F12/00 , G06F17/30
摘要： PURPOSE: To provide a data base device and a data retrieval method which eliminate a need of taking out all of individual difference information between data bases in two generations due to data update work and easily extract difference information. CONSTITUTION: At least two data items are taken as one set to define a related item table showing their relations based on data base structure definition information by a related item table definition part 31, and a change relation table showing the inter-item causalities which are changed at the time of changing the contents of a prescribed data item is defined based on procedures of data update work for design work by a change relation table definition part 32. Data before the change and data after the change are stored in storage devices 6 and 7, and difference information in the change position between data before the change and data after the change is extracted based on the related item table and the change relation table by a retrieval control part 33.

6. 发明专利

JP2002057727A SEMICONDUCTOR INTEGRATED CIRCUIT AND OPTICAL COMMUNICATION MODULE 失效
公开(公告)号：JP2002057727A
公开(公告)日：2002-02-22
申请号：JP2000242618
申请日：2000-08-10
申请人： HITACHI LTD
发明人： KATO TAKAHIRO , UENO SATOSHI , WATANABE KEIKI , TAKAI ATSUSHI
IPC分类号： H04J14/08 , H04B10/035 , H04B10/07 , H04B17/00 , H04B17/19 , H04B17/29 , H04L1/24 , H04L25/02
摘要： PROBLEM TO BE SOLVED: To provide an optical communication module that integrates a transceiver circuit mounted on itself as an integrated circuit without using a discrete component such as a loopback IC, whose operation test and adjustment can easily be conducted, and that provides ease of module design. SOLUTION: The semiconductor integrated circuit (100) for communication of this invention is provided with a reception circuit section (100) that demultiplexes serial signal of a plurality of multiplexed signals received from the outside into signals of each channel, outputs them to the outside, and detects a change in the received signals to generate a clock signal, and with a transmission circuit section (120) that applies time division multiplexing to the serial signals of channels received from the outside and outputs the resulting signals to the outside, is provided with a loopback path (170) that feeds back the signals demultiplexed by the reception circuit section to a transmission line on the input side of the transmission circuit section and with selectors (161, 162) that can switch the signal line to the loopback path.

7. 发明专利

JPH09200167A SYSTEM AND DEVICE FOR OPTICAL PARALLEL TRANSMISSION 失效
公开(公告)号：JPH09200167A
公开(公告)日：1997-07-31
申请号：JP631296
申请日：1996-01-18
申请人： HITACHI LTD
发明人： FUKASHIRO YASUYUKI , HANATANI SHOICHI , TAKAI ATSUSHI
IPC分类号： H04B10/03 , H04J3/00 , H04J3/04 , H04L7/08 , H04B10/02
摘要： PROBLEM TO BE SOLVED: To eliminate the need for an external high speed clock supply source and a clock multiplier circuit by configuring a multiplexer circuit and a demultiplexer circuit with a specific latch circuit and a selector only. SOLUTION: Input data signals D0, D1 at a transmission speed whose phases are not coincident are latched at a trailing of a clock signal by D latches 121-124 of a multiplexer circuit to make the phases are matched with each other. The data signal D1 is latched at a rising of a clock signal by a latch 125 and the phase of the signal D1 is delayed by 1/2-bit. Outputs of the D latches 123, 125 depend on the level of the clock signal by a selector 126. Then one data signal distributed by a demultiplexer circuit is latched by a trailing of a clock signal at D latches 164, 165 and the other data signal is latched at a leading of the clock signal by D latches 161, 162. Furthermore, an output signal of the D latch 162 is latched at a trailing of the clock signal by using the D latch 163 to recover the signals D0, D1 whose phases are arranged.

8. 发明专利

JPH098739A BURST LIGHT RECEPTION CIRCUIT 失效
公开(公告)号：JPH098739A
公开(公告)日：1997-01-10
申请号：JP14893195
申请日：1995-06-15
申请人： HITACHI LTD
发明人： HORIGOME AKIYOSHI , IRIE HIRONORI , TAKAI ATSUSHI
IPC分类号： H03K5/125 , H04B10/2507 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/69 , H04L25/03 , H04B10/28 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/26
摘要： PURPOSE: To exactly perform the pulse reproduction of burst light by setting an optimum threshold voltage without depending on the fluctuation of a light reception level and the change of an input signal pattern. CONSTITUTION: An input signal and a reference potential are added by an adder 1 and inputted to a comparator 6. An adder 2 adds the reference potential and the input signal as well. The output of the adder 2 is inputted through a low-pass filter 5 to the comparator 6 as the threshold voltage. Since the level of the input signal to be superimposed on the reference input side of the comparator is controlled by the adders 1 and 2, the threshold voltage not depending on the fluctuation of a light reception level and the change in the pattern of the input signal can be set and the pulse of burst light can be exactly reproduced.

9. 发明专利

JPH08190037A ALIGNING AND ASSEMBLING METHOD 失效
公开(公告)号：JPH08190037A
公开(公告)日：1996-07-23
申请号：JP101295
申请日：1995-01-09
申请人： HITACHI LTD
发明人： TONEHIRA KOUICHIROU , MIURA ATSUSHI , KANEKO SATOSHI , TAKAI ATSUSHI
IPC分类号： G02B7/00 , G02B27/62
摘要： PURPOSE: To reduce the deviation of an optical axis between an optical element array and a lens array and to reduce optical coupling loss in assembly by making the optical axis of the objective lens of an image processor and the plane of the lens array vertical. CONSTITUTION: A laser light aligned with the optical axis of the objective lens 1 of the image processor 8 is radiated from a laser light source 13. The spot 16 of the laser light reflected by a half mirror 14, reflected by a mirror 15 and passing through the half mirror 14, and the spot 17 of the laser light passing through the half mirror 14, reflected by the lens array 10 and reflected by the half mirror 14 are observed through a finder 2. A chucking jig 5 is adjusted so that the spots 16 and 17 are aligned and the optical axis of the lens 1 and the plane of the lens array 10 are made vertical. Thereafter, the alignment of the optical axis is performed by an X-Y moving stage 7 while monitoring the processor 8, and a lens array holding body 9 and an optical element holding body 6 holding the optical element array 12 are coupled.

10. 发明专利

JPH08160242A OPTICAL FIBER ARRAY 失效
公开(公告)号：JPH08160242A
公开(公告)日：1996-06-21
申请号：JP30784594
申请日：1994-12-12
申请人： HITACHI CABLE , HITACHI LTD
发明人： MURAKAMI KAZUYA , KAJIYAMA SHINICHI , ABE HIDEKAZU , TAKAI ATSUSHI
IPC分类号： G02B6/24 , G02B6/40
摘要： PURPOSE: To provide an optical fiber array which eliminates the need for skew adjustments and can be connected directly to a connector such as an MT connector and an MPO connector. CONSTITUTION: The optical fiber array constituted by arraying plural optical fibers 33 has one-side optical fibers 33 array and fixed on a V-groove substrate 31 where plural V grooves 32 are formed and the other inserted and fixed in a resin body 40 having a hole for arraying the optical fibers 33.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式