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    • 4. 发明专利
    • LOGICAL CIRCUIT
    • JPS59229925A
    • 1984-12-24
    • JP10413883
    • 1983-06-13
    • HITACHI LTDNIPPON TELEGRAPH & TELEPHONE
    • TAKAI ATSUSHIYUMOTO OSAMUHIRAYAMA MASAHIROIDA MASAO
    • H03K19/0952H03K19/094H03K19/0944
    • PURPOSE:To obtain a logical circuit which can attain a high yield, low power consumption and highly integrated structure by using an FET having the threshold voltage of larger absolute value than the logical amplitude of output as a current/voltage conversion resistance of a current switch type logical circuit. CONSTITUTION:A current/voltage conversion element is formed with MOSFET4' and 5' having gates and sources connected to each other for a current switch type logical CML circuit consisting of a normally-on type FET. For instance, an input 100 is defined as the reference voltage Vref, and FET2 and 3 are turned on and off respectively if an input 101 is higher than the voltage Vref. Thus outputs 200 and 201 are set at 1 and 0 respectively. When the output 101 is lower than the Vref, the outputs 201 and 200 are set at 1 and 0 respectively. In this case, the absolute value of the threshold voltage of the FET4' and 5' is set larger than a logical amplitude respectively and used in a non-saturated area. Thus the current of a constant current source 1 can be reduced, and the constant current has virtually no change despite the variance of the FET2 and 3. This attains the low power consumption and a high yield.