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1. 发明专利

JPH03153136A FRAME PHASE CONVERSION METHOD AND FRAME PHASE CONVERSION CIRCUIT 失效
公开(公告)号：JPH03153136A
公开(公告)日：1991-07-01
申请号：JP29099789
申请日：1989-11-10
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKATORI MASAHIRO , NAKANO YUKIO , ISHIDA KEIICHI , MORI TAKASHI , ASHI MASAHIRO , SUGANO TADAYUKI , UEDA HIROMI
IPC分类号： H04J3/00 , H04J3/06 , H04L7/00 , H04Q11/04
摘要： PURPOSE:To warrant TSSI(Time Slet Sequence Integrity) between signals via a same transmission line by using a control method for phase conversion buffer between plural signals in common and selecting a sole state for stuffing no phase conversion buffer to transmit plural signals while keeping mutual frame phase difference. CONSTITUTION:A memory is divided into an ES and a buffer and one memory overrides clocks. Then analog discrimination as to whether or not twice reading or skip of the ES for wonder absorption is to be executed is implemented by one phase comparator. Thus, stuff is generated simultaneously in AU-32#1-#3 and the stuffing is executed at a post-stage buffer. Thus, the transmission is attained while providing a frame phase among the AU-32. Moreover, independent frame phase conversion is attained to an input signal having an independent frame phase.

2. 发明专利

JPH10322300A FRAME PHASE CONVERSION CIRCUIT, CROSS CONNECT DEVICE AND RECEIVER 失效
公开(公告)号：JPH10322300A
公开(公告)日：1998-12-04
申请号：JP10079498
申请日：1998-04-13
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKATORI MASAHIRO , NAKANO YUKIO , ISHIDA KEIICHI , MORI TAKASHI , ASHI MASAHIRO , SUGANO TADAYUKI , UEDA HIROMI
IPC分类号： H04J3/00 , H04J3/06 , H04J3/07 , H04L7/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To warrant time sequence between signals through a same transmission line by adopting a control method of a phase conversion buffer among plural signals in common, making a difference between a write address and a read address between buffers constant while no stuffing is made to the phase conversion buffer so as to transmit plural signals while keeping a frame phase difference. SOLUTION: A demultiplexer section 1 demultiplexes an STM-1 frame into three AU-32 and gives them to highways 32-34. A memory is divided into ES2-4 and buffers 11-13, and a clock signal is replaced in one memory. Then a phase comparator section 7 makes analog discrimination as to whether or not twice- reading or skipped reading of the ES to absorb wondering is to be executed, stuff bits are produced simultaneously in the AU-32#1-#3, stuffing is executed in post-stage buffers 11-13 and transmission is attained while arranging frame phases between the AU-32. Furthermore, independent frame phase conversion is attained for an input signal having an independent frame phase.

3. 发明专利

JPH06141013A METHOD AND CIRCUIT FOR SWITCHING NO-HIT TRANSMISSION LINE 失效
公开(公告)号：JPH06141013A
公开(公告)日：1994-05-20
申请号：JP28577392
申请日：1992-10-23
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKATORI MASAHIRO , NAKANO YUKIO , ASHI MASAHIRO , SUGANO TADAYUKI , KOGURE KOJI , KATAOKA HIDEKI
IPC分类号： H04J3/00 , H04J3/06 , H04J3/07 , H04L1/22 , H04L7/00 , H04L7/027
摘要： PURPOSE:To switch a frame phase conversion circuit in current use to a spare frame phase conversion circuit without generating hit when a transmission line is composed of redundancy constitution by making the output of the frame phase conversion circuit in current use coincide with that of the spare frame phase conversion circuit compulsorily by using pulse stuffing. CONSTITUTION:The frame phase detecting part 5-1 of the frame phase conversion circuit 31 in current use detects the frame phase of a VC-4 in a reception STM-1 frame by reading by a pointer, and stores a signal 16-1 representing the frame phase of the VC-4 in a buffer 1-1. Thence, clock switching for the signal 16-1 representing the frame phase of a reception VC-4 is performed by reading out by a CLK2. Furthermore, difference between an output signal 17-2 and a device frame phase 21-1 is counted by a counter 20-1, and output 22-1 is sent to a conversion circuit 32. Similar processing is performed on a signal 16-2 representing the frame phase of the reception VC-4 at the circuit 32. Thereby, the output frame of the circuit 31 can coincide with that of the circuit 32, and the circuit in current use can be switched to the spare circuit by a selector without generating the hit.

4. 发明专利

JPH03214891A METHOD AND DEVICE FOR CONNECTING TIME DIVISION MULTIPLE SPEED CIRCUIT 失效
公开(公告)号：JPH03214891A
公开(公告)日：1991-09-20
申请号：JP812090
申请日：1990-01-19
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NAKANO YUKIO , SUGANO TADAYUKI , TAKATORI MASAHIRO , UEDA HIROMI
IPC分类号： H04J3/22 , H04J3/00 , H04J3/16 , H04Q11/04
摘要： PURPOSE:To attain a circuit connection for which delay is little even when the circuits of plural speeds coexist by variably controlling a switching cycle in time division corresponding to the circuit speed with the use of a memory storing the circuit speed. CONSTITUTION:The time division multiple signalization signal of an input highway 300 is written to a data memory 102. On the other hand, in a rotational speed control memory 100, the circuit speed information of the circuit of the memory 102 is stored on an output highway 301. Besides, in an address control memory 101, circuit connection information is stored. From the memory 100, the speed information of the circuit is read in time division for each time slot and is supplied to a control address generating part 201 and a data memory address generating part 202. In the address generating part 201, an reading address is generated based on the information from the memory 100 and supplied to the memory 101. Based on the reading address of the memory 101, the address generating part 202 generates the reading address of the memory 102 and supplies it to the memory 102.

5. 发明专利

JPH02272925A METHOD AND CIRCUIT FOR SYNCHRONIZING FRAME PHASE BY POINTER CONVERSION 失效
公开(公告)号：JPH02272925A
公开(公告)日：1990-11-07
申请号：JP9302289
申请日：1989-04-14
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKATORI MASAHIRO , NAKANO YUKIO , SUGANO TADAYUKI , UEDA HIROMI
IPC分类号： H04J3/00 , H04J3/06 , H04L7/00
摘要： PURPOSE:To decrease the ineffective part of a data signal by setting the value of a pointer for a transmitted frame within one frame after the value of the pointer for a received frame is changed. CONSTITUTION:A frame memory 1, write control circuit 2, read control circuit 3, pointer detection circuit 4, pointer buffer 5, selector 6, selector control circuit 7, reception side frame counter 8, transmission side frame counter 9, down counter 30, buffer 31 for address storage and comparator 32 are provided. Even when the value of the pointer in the received frame is changed, phase difference with the new pointer is detected before the pointer of the transmitted frame is generated. Accordingly, the new pointer value is generated in one frame, namely, after the phase difference between the received frame and transmitted frame. Thus, the ineffective part of communication data can be decreased.

6. 发明专利

JPH0350927A FRAME ALINGER AND ITS CONTROL METHOD 失效
公开(公告)号：JPH0350927A
公开(公告)日：1991-03-05
申请号：JP18468389
申请日：1989-07-19
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ASHI MASAHIRO , SUGANO TADAYUKI , TAKATORI MASAHIRO , UEDA HIROMI
IPC分类号： H04J3/06 , H04L7/00
摘要： PURPOSE:To attain the frame alignment while warranting the time sequence by providing an individual phase memory, a common phase memory and a belonging memory and referencing the memories so as to select a write start phase. CONSTITUTION:Low speed frames are sent in the order of frames A-D while being subject to byte multiplex. Then an address to the frames A-D is given to an individual phase memory 7 and a belonging memory 9 according to a value of a frame counter 10. The memory 9 has an address of a common phase memory 8 referenced by each low speed frame and gives a value of the address designated in the memory to the address of the memory 8. Thus, the values of the memories 7, 8 for each low speed frame are recognized by a control section 6 and the content of the memories 7, 8 is updated according to a prescribed operation based on slip production information detected by a phase comparator 5. According to the operation above, the frame alignment is executed by the multiplex processing while warranting the time sequence with the operation as above.

7. 发明专利

JPS6485452A AIS SIGNAL DETECTION CIRCUIT 失效
公开(公告)号：JPS6485452A
公开(公告)日：1989-03-30
申请号：JP24070787
申请日：1987-09-28
申请人： HITACHI LTD
发明人： ASHI MASAHIRO , SUGANO TADAYUKI
IPC分类号： H04L29/14 , H04L13/00 , H04L25/02
摘要： PURPOSE:To surely detect an AIS signal even when data error exists by receiving 0 detection/undetection information from a monitoring storage means and deciding it as the detection of an AIS signal when the number of signal lines detecting 0 in the n-line of signal lines is a specified number or below. CONSTITUTION:A control means 2 generates a timing signal deciding a monitoring range and controls the entire operation of an AIS(Alarm Indication Signal) signal detection circuit. Monitoring storage means 11-14 receive a timing signal from the control means 2 to monitor whether or not the signal 0 is received at every signal in the n-parallel signal in the monitoring range and stores it till the next monitoring range is started newly when it is received. A deciding means 1 receives the 0 detection/undetection information for n-set of signals from the monitoring storage means 11-14 and decides it as the reception of the AIS signal when the number of signal lines detecting 0 is the prescribed number or below and it is outputted externally. Thus, some degree of data error is allowed to detect the AIS signal.

8. 发明专利

JPS63292841A FRAME SYNCHRONIZING SYSTEM 失效
公开(公告)号：JPS63292841A
公开(公告)日：1988-11-30
申请号：JP12713487
申请日：1987-05-26
申请人： HITACHI LTD
发明人： ASHI MASAHIRO , NAKANO YUKIO , SUGANO TADAYUKI
IPC分类号： H04J3/06 , H04L7/08
摘要： PURPOSE:To prevent fixed data from being detected erroneously, by constituting a frame synchronization pattern of a fixed pattern consisting of the same bit series at every frame and a transitional pattern consisting of a bit series changing at every frame in a specific cycle, in a digital communication equipment. CONSTITUTION:When a frame counter 2 steps, arriving at a phase to detect the frame synchronization pattern, and a frame synchronization detecting signal is outputted from the frame counter 2 to a coincidence/discrepancy decision circuit 6, the coincidence/discrepancy of the frame synchronization pattern is decided. A synchronization protection circuit 7 outputs a hunting operation instruction signal to the coincidence/discrepancy decision circuit 6, the frame counter 2, and a fransitional pattern generation circuit 4 when receiving a signal representing the discrepancy, then, an operation is shifted to a hunting operation state. On the other hand, when the signal representing the coincidence is received, the completion of a protection operation at a rear side is decided after the bit series to be outputted to a comparator 5 being stepped by one by shifting the operating phase of the transitional pattern generation circuit 4.

9. 发明专利

JPS6294030A HIGH-ORDER GROUP TRANSMISSION SYSTEM 失效
公开(公告)号：JPS6294030A
公开(公告)日：1987-04-30
申请号：JP23353685
申请日：1985-10-21
申请人： HITACHI LTD
发明人： SUGANO TADAYUKI , MIYANO YOSHIHIKO , FUJITA HIROYUKI
IPC分类号： H04J3/06
摘要： PURPOSE:To decrease the delay time by multiplexing all 2nd order group trans mission bits and arranging synchronizing frame bits scatteringly at every frame length/N so as to decrease the memory capacity for phase matching. CONSTITUTION:Frame synchronizing is bits F1-F4 consisting of u-bit respective ly are arranged scatteringly to divide one frame length, i.e., a time T0, into 4 equally. The 2nd order group signals D1-D4 subjected to time division multi plex are formed to have the arrangement of multiplex unit V, that is, n-time repetition of up to m-set 2nd order group signal input number subjected to sequential multiplex in the information unit of 8-bit normally. When the 2nd order group signal P has, e.g., 789-bit, q=11-bit is added as an excess bit and time division multiplex is applied by a multiplexer 1 from the signal 10 of 800-bit number to generate the 3rd or 4th order group signal 11. In adopting the frame constitution as above and inputting the signal to a line edit equipment 24, the signals 12, 13 require the delay by T1, Tn to a reference frame 27, but are enough for the delay of T0/4 only at most to the time t0 and the memory capacity is saved.

10. 发明专利

JPS61147625A TRAIN INFORMATION BROADCASTING SYSTEM 失效
公开(公告)号：JPS61147625A
公开(公告)日：1986-07-05
申请号：JP26830584
申请日：1984-12-21
申请人： HITACHI LTD
发明人： SUGANO TADAYUKI
IPC分类号： H04H20/00 , H04H20/62 , H04R27/00
摘要： PURPOSE:To distinguish troubles of acoustic devices and troubles of a PCM device itself from each other in a central station by communicating in two directions on a PCM line between terminal station repeating parts and providing an information turning-back means in a speaker interface of each terminal station repeating part. CONSTITUTION:Train information from the central station is read out by a PCM branching device of a station and is transmitted to a speaker interface (IF) 6 through a train information receiving line 9 and is broadcast through a relay contact 15. When earth information is read out similarly, an earth signal is transmitted from the device 5 to a signal receiving line 13 and is inputted to a relay 14 to switch contacts 15 and 16. Therefore, train information is turned back to the device by a train information transmitting line 10. The earth signal is transmitted to the device 5 through a signal transmitting circuit 12, and both signals are transmitted to the central station and are condirmed in a monitor part 2.

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