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1. 发明专利

JPH03249842A ATM EXCHANGE AND ADAPTATION PROCESSOR 失效
公开(公告)号：JPH03249842A
公开(公告)日：1991-11-07
申请号：JP22135190
申请日：1990-08-24
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KUNIMOTO MASAO , ICHIKAWA HIROYUKI , KASHIO JIRO , KAWAKITA KENJI , GOHARA SHINOBU , IWAKI SHINICHI
IPC分类号： H04L29/04
摘要： PURPOSE:To simultaneously execute an ADP processing for plural layer 2 processing parts by constituting the second FIFO(first-in first-out) of a reassembly processing FIFO by means of plural FIFO and error processing abolishment FIFO at every layer 2 processing part. CONSTITUTION:FIFO is formed by dividing a reassembly memory 140 in an ADP(adaptation layer) processing part into buffers in terms of a cell (cell buffer) and they are chained. FIFO is constituted of plural first FIFO 141 for assembling a frame, a second FIFO 142 composed of plural FIFO at every layer 2 processing part for waiting for transmission for the layer 2 processing part and an abolishment FIFO for reproducing the cell buffer when an error is detected in the middle of a reassembly processing, and an idle FIFO 143 for waiting for the reception of the cell. Thus, the ADP processing for plural layer 2 processing parts can simultaneously be executed.

2. 发明专利

JPS6268393A DIAL SIGNAL CONVERTING EQUIPMENT 失效
公开(公告)号：JPS6268393A
公开(公告)日：1987-03-28
申请号：JP20654085
申请日：1985-09-20
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEMURA TETSUO , IWAKI SHINICHI , GOHARA SHINOBU , SAKAI YOICHI , SHINOOKA MAKOTO , KOIKE HIDEYUKI
IPC分类号： H04Q1/50
摘要： PURPOSE:To improve an S/N and to decrease the malfunction of a multi-frequency signal receiver by connecting a four-line channel to a host system, removing the dial pulse of a subscriber at a two-line side and inserting a multi-frequency signal corresponding to a receiving dial pulse from a four-line side. CONSTITUTION:By the oscillation of a DP telephone set 5 by the subscriber, an audio response unit 9 is descended from the guidance, sent to a telephone line EF and arrives at the DP telephone set 5 through the two-line four-line converting circuit 1 of a signal converting device 7 and an A line and a B line. When the member number is dialed in accordance with the guidance, the number comes to be the loop interrupting signal of the A line and B line and counted by a counting control circuit 2. The counting control circuit 2 sends a selecting changing-over signal to selecting circuits 4C and 4D through a reed 12 at every time one digit of the figure is received, and the source of the calling signal to an ascending call line C line and D line is changed over from four-line outputs 15 and 16 to the outputs 13 and 14 of an oscillating circuit 3. When the counting control circuit 2 sends the driving signal through a reed 11 to the oscillating circuit 3, the corresponding multi-frequency signal is outputted to reeds 13 and 14, and then, the circuit arrives at the multi-frequency signal receiving equipment 8 and received through the C line and D line.

3. 发明专利

JPS6268356A INPUT CONFIRMING SYSTEM 失效
公开(公告)号：JPS6268356A
公开(公告)日：1987-03-28
申请号：JP20653985
申请日：1985-09-20
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IWAKI SHINICHI , TAKEMURA TETSUO , GOHARA SHINOBU , SAKAI YOICHI , SHINOOKA MAKOTO , KOIKE HIDEYUKI
IPC分类号： H04M3/42
摘要： PURPOSE:To confirm the inputted information in the unit of blocks by sending a voice corresponding to the received character string at each section of blocks to the character string inputted from the user. CONSTITUTION:In order to designate a facsimile confidential communication, '1' is dialed at first according to the numbering system. The number is received by a PB reception circuit 46 connected to the operating talking line in an IRE 4 and when a controller 42 receives the notice, the circuit 46 receives the dial number, then number system information stored in a storage device 43 is read and referenced, recognized and held. Succeedingly, when a dial number 2 is received by the PB reception circuit 46, the end of reception of a block being a communication identification code is recognized, a voice signal corresponding to a dial number 12 is read sequentially from a voice buffer circuit 44 and sent to the user 1 as a voice (a) via a voice transmission circuit 45. The user 1 listens to the voice to confirm the correct input.

4. 发明专利

JP2000232696A SWITCHING SYSTEM 失效
公开(公告)号：JP2000232696A
公开(公告)日：2000-08-22
申请号：JP2000032723
申请日：2000-02-04
申请人： HITACHI LTD
发明人： SAKURAI YOSHITO , GOHARA SHINOBU , OTSUKI KANEICHI , KATO TAKAO , KUWABARA HIROSHI
IPC分类号： H04Q3/545 , H04L12/70 , H04L12/931 , H04L12/947 , H04L12/951 , H04M3/00 , H04Q11/04 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To reduce cost and to improve processing capacity by converting information received from a relay line into a fixed length packet to which a header including destination information is added, transmitting the packet to a central switching module, autonomously switching the module by using the fixed length packet as a unit, and then converting a peripheral switching module around the destination into the original information by removing the header of the fixed length packet. SOLUTION: A time switch 501 rearranges a time division multiplex signal inputted from a subscriber's line in each destination module in accordance with an instruction from a control circuit 503. A link interface 502 adds a header such as a destination address to the rearranged signal and sends the signal to a central switching module 101. Each link interface 504 reads out the header of each time slot, executes non-block processing on the time slot and then sends the processed time slot to each time switch 507. The header is removed from each time slot outputted from the module 101 and the signal is written in a time switch 510 by an address instructed by a control circuit 508 according to information included in the header.

5. 发明专利

JP2000151616A ATM SPEECH PATH UNIT 失效
公开(公告)号：JP2000151616A
公开(公告)日：2000-05-30
申请号：JP36912999
申请日：1999-12-27
申请人： HITACHI LTD
发明人： TORII YUTAKA , SAKURAI YOSHITO , MORI MAKOTO , GOHARA SHINOBU , OTSUKI KANEICHI
IPC分类号： H04L12/813 , H04L12/28 , H04L12/911 , H04L12/931
摘要： PROBLEM TO BE SOLVED: To provide the asynchronous transfer mode ATM communication unit with a simple configuration where a cell stream control is attained by monitoring whether or not traffic of a received cell is not violated against an application value. SOLUTION: The ATM communication unit that receives/outputs a cell of a fixed length consisting of a header part and an information part and applies communication processing to the cell based on the information of the header part of the cell is provided with a plurality of input output line interface sections that receive/output cells of a fixed length, and a switch section 110 that interconnects the plurality of the input output lien interface sections to transfer the received cell of a fixed length to any of output line interface sections that is a destination, and each of the input output lie interface sections provided with a header detection circuit that detects a header of the received cell, a table that stores communication processing control information corresponding to an input identification number of the header, and a monitor circuit that measures a cell flow rate received for each input identification to monitor whether or not the flow rate exceeds a specified value stored in the table.

6. 发明专利

JPH1084363A ATM SWITCH 失效
公开(公告)号：JPH1084363A
公开(公告)日：1998-03-31
申请号：JP21162397
申请日：1997-08-06
申请人： HITACHI LTD
发明人： YANAGI JUNICHIRO , TAKASE MASAHIKO , OZAKI NAOHIKO , GOHARA SHINOBU
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To output cells arrived in a burst way while arranging them uniformly, to control a frequency band and to avoid an increase in a buffer amount for frequency band control by using a common buffer type memory switch having a list structure for each virtual path identifier. SOLUTION: A buffer control section 2 is provided with a chain write address table 22 to form a list structure for each virtual path identifier(VPI), a band counter 26 and a band table 27 to obtain the VPI for an output this time, and a read address table 28 using the VPI to read an output cell from a buffer memory 12 to configure a common buffer memory switch for frequency band control. Thus, outputs OUT at an equal interval are obtained from a cell input IN arrived in a burst way and the buffer memory 12 possessed substantially by the switch is used in common for a memory required for the frequency band control so as to decrease number of buffers.

7. 发明专利

JPH1070535A ATM SWITCH AND ITS CONTROL METHOD 失效
公开(公告)号：JPH1070535A
公开(公告)日：1998-03-10
申请号：JP21162497
申请日：1997-08-06
申请人： HITACHI LTD
发明人： YANAGI JUNICHIRO , TAKASE MASAHIKO , OZAKI NAOHIKO , GOHARA SHINOBU
IPC分类号： H04L12/28
摘要： PROBLEM TO BE SOLVED: To conduct frequency band control by using a buffer type memory having a list structure for each VPI and extracting an output cell from an outgoing channel of an outgoing channel counter in the cell sequence so as to uniformly arrange cells arrived in a burst way. SOLUTION: Cells from inputs 501-1-36 are multiplexed by an MUX11 and stored to a buffer memory BFM12. On the other hand, routing information RTG is decoded by a routing recorder RTDEC21 of a buffer control section 2 to designate corresponding chain write address tables 22-1-36. Then a virtual path identifier VPI of the arrived cells is referenced to generate a list structure. In the case of reading cells, an outgoing channel of an outgoing channel counter 24 are fed to an outgoing channel decoder 25 and one of band counters 26-1-36 is selected and band tables 27-1-36 are referenced and an output cell is extracted from the BFT12 and demultiplexed by a DEMUX13 and outputted. Thus, cells arrived in a burst way are uniformly arranged.

8. 发明专利

JPH09205443A METHOD FOR CONSTITUTING FIXED LENGTH PACKET 失效
公开(公告)号：JPH09205443A
公开(公告)日：1997-08-05
申请号：JP28800496
申请日：1996-10-30
申请人： HITACHI LTD
发明人： SAKURAI YOSHITO , GOHARA SHINOBU , OTSUKI KANEICHI , KATO TAKAO
IPC分类号： H04Q11/04 , H04L12/28 , H04L12/64
摘要： PROBLEM TO BE SOLVED: To provide a method for constituting a fixed length packet suitable for integrating the various kinds of information such as sound and data and performing exchange. SOLUTION: After editing line exchange information from a subscriber's line or a relay line or packet exchange information in the information part of a fixed length, the fixed length packet for which at least a fixed length packet using state identifier, the information kind identifier of the fixed length packet to be transmitted and received, an origination side equipment identifier, a destination equipment identifier and a destination identifier corresponding to the information of the fixed length packet to be transmitted and received are added to each information part 302 of the fixed length as a header 301 is constituted. Thus, a communication equipment processes the line exchange information of the sound or the like with less delay time by the header added to the respective fixed length packets and processes packet information provided with a burst property of the data or the like by using the same speech path and a highly efficient economical exchange system is realized regardless of the scale.

9. 发明专利

JPH09191325A DISTRIBUTION TYPE EXCHANGE SYSTEM 失效
公开(公告)号：JPH09191325A
公开(公告)日：1997-07-22
申请号：JP26159596
申请日：1996-10-02
申请人： HITACHI LTD
发明人： SAKURAI YOSHITO , GOHARA SHINOBU , OTSUKI KANEICHI , KATO TAKAO , KUWABARA HIROSHI
IPC分类号： H04Q3/545 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/951 , H04Q3/00 , H04Q11/04 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a distribution type exchange system with excellent extending performance from a small scale up to a large scale suitable or high speed broad band communication and with high information exchange performance economically with a periodic performance. SOLUTION: This system is provided with plural peripheral exchange modules 102-109 operated independently of each other and having a call processing means including a call processing processor conducting call processing in response to information from a subscriber line and a relay line, a central exchange module 101 having a self routing switch conducting automonous exchange of information, and a synchronization transmission line sending/receiving a frame signal with a prescribed period having plural time slots. The peripheral exchange modules 102-109 convert information from the subscriber line and the relay line into a fixed length packet with a header including information destination and send the packet to the central exchange module 101 via a time slot, then the central exchange module 101 applies automonous exchange the fixed length packet to the peripheral exchange modules 102-109 being the information destination based on the content of the header.

10. 发明专利

JP2586388B2 失效
公开(公告)号：JP2586388B2
公开(公告)日：1997-02-26
申请号：JP22986093
申请日：1993-09-16
申请人： HITACHI LTD
发明人： SAKURAI YOSHITO , GOHARA SHINOBU , OOTSUKI KANEICHI , KATO TAKAO , KUWABARA HIROSHI
IPC分类号： H04M3/00 , H04L12/70 , H04Q3/545 , H04Q11/04 , H04L12/56

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