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1. 发明专利

JPH03249842A ATM EXCHANGE AND ADAPTATION PROCESSOR 失效
公开(公告)号：JPH03249842A
公开(公告)日：1991-11-07
申请号：JP22135190
申请日：1990-08-24
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KUNIMOTO MASAO , ICHIKAWA HIROYUKI , KASHIO JIRO , KAWAKITA KENJI , GOHARA SHINOBU , IWAKI SHINICHI
IPC分类号： H04L29/04
摘要： PURPOSE:To simultaneously execute an ADP processing for plural layer 2 processing parts by constituting the second FIFO(first-in first-out) of a reassembly processing FIFO by means of plural FIFO and error processing abolishment FIFO at every layer 2 processing part. CONSTITUTION:FIFO is formed by dividing a reassembly memory 140 in an ADP(adaptation layer) processing part into buffers in terms of a cell (cell buffer) and they are chained. FIFO is constituted of plural first FIFO 141 for assembling a frame, a second FIFO 142 composed of plural FIFO at every layer 2 processing part for waiting for transmission for the layer 2 processing part and an abolishment FIFO for reproducing the cell buffer when an error is detected in the middle of a reassembly processing, and an idle FIFO 143 for waiting for the reception of the cell. Thus, the ADP processing for plural layer 2 processing parts can simultaneously be executed.

2. 发明专利

JPH11317740A ATM SWITCHBOARD 失效
公开(公告)号：JPH11317740A
公开(公告)日：1999-11-16
申请号：JP2965199
申请日：1999-02-08
申请人： HITACHI LTD
发明人： KUNIMOTO MASAO , KASHIO JIRO , MORI MAKOTO , GOHARA SHINOBU
IPC分类号： H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide a very economical exchange system by efficiently arranging a signal device having constitution suitable to the ATM switchboard in an ATM exchange system. SOLUTION: The ATM switchboard which switches cells of fixed length is equipped with a switch means 30 which is equipped with input lines and output lines and transfers cells inputted from the respective input lines to some output lines specified with header information of the cells, a signal processor which is connected to a specific output line of the switch means 30, and a processor 40 for switching control which is coupled with the signal processor; and cells for control which are inputted from the respective input lines are transferred by the switch means 30 to the specific output lines and converted by the signal processor into a signal frame, which is passed to the post-processor 40.

3. 发明专利

JPH1146200A ATM EXCHANGE 失效
公开(公告)号：JPH1146200A
公开(公告)日：1999-02-16
申请号：JP13937398
申请日：1998-05-21
申请人： HITACHI LTD
发明人： KUNIMOTO MASAO , KASHIO JIRO , MORI MAKOTO , GOHARA SHINOBU
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To efficiently arrange a signal device in an asynchronous transfer mode(ATM) exchange system and to improve the excellence in economicity and reliability by installing a subscriber line signal device on a trunk line side of an ATM switch. SOLUTION: An subscriber line signal device 1 which consists of an ADP processing part 100 which performs adaptation processing such as segmentation and reassembling and an ALPD LSI 101 (101-1 to 101-2) which performs layer 2 protocol processing of a signal channel is connected to a trunk line side of an ATM switch 30 through a bus 15. In this way, by installing the device 1 in an ATM exchange system on a trunk line side of the switch 30 and installing the part 100 to each subscriber line in common, a cell separating/inserting circuit of every subscriber line and buses and a multiplexing/separating circuit for line concentration and distribution can be ignored and therefore, it is possible to reduce a hardware amount.

4. 发明专利

JPH08331155A ATM EXCHANGE 失效
公开(公告)号：JPH08331155A
公开(公告)日：1996-12-13
申请号：JP16142896
申请日：1996-06-21
申请人： HITACHI LTD
发明人： KUNIMOTO MASAO , KASHIO JIRO , MORI MAKOTO , GOHARA SHINOBU
IPC分类号： H04Q3/00 , H04L12/28
摘要： PURPOSE: To reduce an amt. of hardware by installing a subscriber line signal device on the side of the repeating line of an ATM switch and installing an ADP processing part in common with each subscriber. CONSTITUTION: By installing a subscriber line signal device 1 including an ADP processing part 100 on the side of the repeating line of an ATM switch 30, the cell of a signal channel is collected and distributed by using the ATM switch 30, and the adaptation processing common to each subscriber line is performed. For the signal from the repeating line, a repeating line signal device including the ADP processing part 100 is installed on the side of the subscriber line of the ATM switch 30. By arranging the ADP processing part 100 on the rearside of the ATM switch and collecting/distributing the cell of the signal channel by the ATM switch, the separation/insertion circuit of the cell and the multiplex/demultiplex circuit of the cell become unnecessary. By executing the common adaptation processing, an amt. of hardware required for the adaptation processing can be reduced.

5. 发明专利

JP2533591B2 失效
公开(公告)号：JP2533591B2
公开(公告)日：1996-09-11
申请号：JP31882487
申请日：1987-12-18
申请人： HITACHI LTD
发明人： NAKAYASHIKI SUSUMU , KASHIO JIRO , HARAKAWA TAKESHI , WADA HIROYUKI , TOTSUGI YOSHINORI
IPC分类号： H04L12/42

6. 发明专利

JP2533550B2 失效
公开(公告)号：JP2533550B2
公开(公告)日：1996-09-11
申请号：JP17095387
申请日：1987-07-10
申请人： HITACHI LTD
发明人： NAKAYASHIKI SUSUMU , KASHIO JIRO , HARAKAWA TAKESHI
IPC分类号： H04L12/437

7. 发明专利

JPH02170646A PACKET CONGESTION CONTROL METHOD AND PACKET EXCHANGE DEVICE 失效
公开(公告)号：JPH02170646A
公开(公告)日：1990-07-02
申请号：JP32330088
申请日：1988-12-23
申请人： HITACHI LTD
发明人： FUKUDA ISAO , KAWAKITA KENJI , KASHIO JIRO , TORII YUTAKA , GOHARA SHINOBU , ENDO NOBORU
IPC分类号： H04Q3/00 , H04L12/801 , H04L12/911
摘要： PURPOSE:To detect congestion at every logical channel by adding information to indicate the congestion to an inputted packet when the congestion is generated in a packet exchange. CONSTITUTION:When the packet congestion is generated inside a switch concerning one of output lines, the congestion display information (simply mentioned as congestion information) is added to the packet directed to the congested output line, and exchange-processed to a target line interface part. When the packets are repeated to transmission interface circuits 170a to 170n, distributing circuits 150a to 150n checks whether or not the congestion information is added to these packets, when the congestion information is added, the packets are fetched, they are converted into congestion notifying packets, and sent to inserter circuits 130a to 130n. Thus, the congestion notifying packets are returned to the switch, and outputted to the line interface connected to a transmission source. The congestion information is added to a header part which is utilized only in the exchange device, and removed when the packets pass through the transmission circuit interface.

8. 发明专利

JPH02140037A ATM EXCHANGE 失效
公开(公告)号：JPH02140037A
公开(公告)日：1990-05-29
申请号：JP15677289
申请日：1989-06-21
申请人： HITACHI LTD
发明人： KUNIMOTO MASAO , KASHIO JIRO , MORI MAKOTO , GOHARA SHINOBU
IPC分类号： H04L29/04 , H04L12/56 , H04L29/06 , H04Q11/04
摘要： PURPOSE:To eliminate the need for a cell separation/insertion circuit and a cell multiplex/demultiplex circuit by arranging an ADP processing section to the rear side of an ATM switch and utilizing the ATM switch so as to collect/ distribute cells for a signal channel. CONSTITUTION:A subscriber line signal device 1 comprising an ADP processing section 100 applying adaptation processing and an LAPD.LSI 101 applying layer 2 protocol processing of a signal channel is connected to a relay line side of the ATM switch 30. The device 1 is connected to a processor 40 applying layer 3 protocol processing of the signal channel, header conversion table revision, initial value setting of a switch 30 and control of the LAPD.LSI 101 or the like. A memory 41 is used for a storage area and a work area for a program executed by a processor 40. A subscriber line interface section 10 and a relay line interface section 20 apply addition/delete of an optical/electric signal and a route information part to each cell or the like respectively.

9. 发明专利

JPH01276850A MAIN STATION COMPETITION CONTROL SYSTEM IN DECENTRALIZED CONTROL NETWORK 失效
公开(公告)号：JPH01276850A
公开(公告)日：1989-11-07
申请号：JP10390988
申请日：1988-04-28
申请人： HITACHI LTD
发明人： NAKAYASHIKI SUSUMU , HARAKAWA TAKESHI , KASHIO JIRO
IPC分类号： H04J3/06 , H04L12/433
摘要： PURPOSE:To prevent the impossibility of a main station determination by confirming the validity of a received competition frame with its own judgement of respective communication terminals (ST). CONSTITUTION:Each ST1 to send a competition frame gives an inherent identifier for a competition frame sent, respective STs to receive the competition frame judge the rationality of a receiving competition frame based on the identifier and determines the action with its own ST in accordance with the judged result. The ST1 is composed of a MAC(medium access control) communication mechanism and a PHY(physical layer control) communication mechanism and the ST to receive the competition frame, when it is superimposed and received by checking the identifier, does not execute the competition control. When a received competition frame includes another sending time identifier of already received competition frame, respective STs maintain the competition control condition. Thus, it is prevented that the main station frame floats and the station is not determined.

10. 发明专利

JPS6236949A MULTIPLE LINE SELECTING SYSTEM 失效
公开(公告)号：JPS6236949A
公开(公告)日：1987-02-17
申请号：JP17581385
申请日：1985-08-12
申请人： HITACHI LTD
发明人： MIZUHARA NOBORU , HOSHI TORU , KASHIO JIRO , MORITA TAKASHI
IPC分类号： H04M3/00 , H04Q3/54
摘要： PURPOSE:To collect the required number of lines for the call handling broad band information requiring plural base lines and to attain efficient acquisition and release by providing an idle line managing memory to a digital exchange applying incorporated exchange of multiple address information. CONSTITUTION:A counter of the number of idle lines ILC representing a present idle line and a time slot number table TNT are provided in an idle line management table ILT of an idle line management memory provided to digital exchange incorporating voice and data. A time slot number corresponding to an idle line is stored in the table TNT altogether and an acquisition/release pointer HIP is provided as a stack pointer. In case of line acquisition, the number of lines and a counter ILC to be acquired are compared at first and when the acquisition is made possible, a time slot of a desired line number is acquired from a position represented by the pointer HIP from the table TNT. Further, the line release is conducted similarly and the required number of lines are acquired and released efficiently altogether.

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