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1. 发明专利

JPH07263468A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND LEAD FRAME 失效
公开(公告)号：JPH07263468A
公开(公告)日：1995-10-13
申请号：JP4745794
申请日：1994-03-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： AKASAKI HIROSHI , OTSUKA KANJI , SHIRAI MASAYUKI , HONDA ATSUSHI , TSUBOI TOSHIHIRO , OKINAGA TAKAYUKI , EMATA KOJI
IPC分类号： H01L21/52 , H01L23/50
摘要： PURPOSE:To prevent cracking of a package which occurs at the time of solder reflowing to mount the package. CONSTITUTION:A die pad 6 of a lead frame to be used to mount a semiconductor chip 3 is formed in a frame state, and a stepped part 6a is formed on an inner periphery of the pad 6. The chip 3 is fixedly fitted into the pad 6.

2. 发明专利

JPH0750361A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0750361A
公开(公告)日：1995-02-21
申请号：JP19327493
申请日：1993-08-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OZAKI HIROSHI , TSUBOI TOSHIHIRO , MIWA TAKASHI , KIKUCHI NORISHIGE , KOSAKU HIROSHI , AKASAKI HIROSHI , KIKUCHI MASAYUKI
IPC分类号： H01L23/12
摘要： PURPOSE:To prevent disconnection of a through hole due to the change of temperature by a method wherein a dummy lead is provided in the through hole, and the lead is soldered in the through hole. CONSTITUTION:At least a through hole 7 is provided on the wiring substrate 1 located in the vicinity of an external lead 6, a dummy lead 8 is inserted into the through hole 7, soldered by solder 9, and the dummy lead 8 is electrically connected and mechanically fixed. The lead such as copper wire, kovar wire and the like, whose diameter is smaller than the inside diameter of the through hole 7 and length is longer than that of the through hole 7, is used as the dummy lead 8. As a result, no discontinuity due to voids is generated even when a temperature cycle test and the like are conducted, and the reliability of products can be improved.

3. 发明专利

JPH05166926A SEMICONDUCTOR SUBSTRATE DICING METHOD 失效
公开(公告)号：JPH05166926A
公开(公告)日：1993-07-02
申请号：JP32855391
申请日：1991-12-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： AKASAKI HIROSHI , OTSUKA KANJI
IPC分类号： H01L21/301 , H01L21/78
摘要： PURPOSE:To provide generation of faulty short-circuit between electrodes, and to improve the reliability of the products by a method wherein the metallizing film on the back side of a pellet located directly under a scribe line, is selectively removed before dicing. CONSTITUTION:The scribe line 4, drawn by patterning on the wiring metal layer 3 of a semiconductor substrate 1, is recognized by a pattern recognition part 5 through a protection film 6, a pulse laser beam 7 is applied to the surface of the backside metallizing layer 2 directly under the scribe line 4, a local laser annealing is conducted, and an alloy layer 9 is formed. Blade sawing is conducted with a diamond blade 8 from above the scribe line 4, and full-cut dicing is conducted as deeply as the groove reaches the alloy layer 9. As a result, even when the sawing blade reaches the back side metallizing film 2, microcrack pieces produced in the vicinity of the end of the groove by dicing in the back side of a pellet are supported by the metallizing film in the back side because the metallizing film 2 has lost metallic mechanical characteristics.

4. 发明专利

JPH0473955A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0473955A
公开(公告)日：1992-03-09
申请号：JP18847890
申请日：1990-07-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUBO KAZUHISA , OTSUKA KANJI , TATE HIROSHI , AKASAKI HIROSHI , KIKUCHI NORISHIGE
IPC分类号： H01L23/04 , H01L21/60 , H01L23/02
摘要： PURPOSE:To improve the humidity resistance of a semiconductor device while improving the relative positioning among a semiconductor chip, a substrate, and a cap by providing the cap with a recess for positioning the chip, and fixing the top of the chip with adhesive in the recess. CONSTITUTION:A semiconductor device includes semiconductor chip 2 that is mounted on a substrate 1, and the chip and substrate are connected through bump electrodes 3. The semiconductor device is sealed by a package cap 4 with brazing material 7. The cap has a recess for positioning the chip, and adhesive 6 (good thermal conductor, preferably) is applied to the recess to bond the top of the chip. For example, the chip is provided with a through hole 8A for supplying insulating filler and a through hole 8B for letting air out. The chip is sealed by the cap, and then insulating silicone filler 9 is charged.

5. 发明专利

JPH0465137A ELECTRONIC DEVICE 失效
公开(公告)号：JPH0465137A
公开(公告)日：1992-03-02
申请号：JP18076390
申请日：1990-07-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： AKASAKI HIROSHI , OTSUKA KANJI
IPC分类号： H01L21/60
摘要： PURPOSE:To lengthen a fatigue life by a method wherein a plurality of external terminals are 'formed at a semiconductor chip or a semiconductor device, a plurality of terminals which are faced with the respective external terminals are formed at a mounting board and both are connected electrically via flexible bonding wires. CONSTITUTION:A stress is exerted on a part between an external terminal 2 of a semiconductor chip 1 and a terminal 11 due to the difference in a coefficient of thermal expansion between the chip 1 and a mounting board 10. The part in which a wire 12 is connected to the external terminal 2 via a brazing material 5 and the part in which the wire 12 is connected to the terminal 11 are fixed more firmly than the strength of wires 12 in parts other than them. As a result, the stress due to the difference in the coefficient of thermal expansion is exerted on the wires 12 in the parts other than the connecting parts. Since the wires 12 in the parts to which the stress is exerted are flexible, they can absorb the stress due to the difference in the coefficient of thermal expansion. Thereby, since it is possible to reduce that the connection of the external terminal 2 to the terminal 11 is set to a disconnection state, the reliability of an electronic device is enhanced.

6. 发明专利

JPH03242963A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03242963A
公开(公告)日：1991-10-29
申请号：JP3824390
申请日：1990-02-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , OTSUKA KANJI , AKASAKI HIROSHI
IPC分类号： H01L23/34 , H01L23/50 , H05K3/34
摘要： PURPOSE:To prevent misregistration of a pin grid array(PGA) readily and surely in surface mounting the PGA by making a part of lead pins of the PGA longer than remaining lead pins and by providing a hole whereto the longer lead pin is inserted on a packaging substrate. CONSTITUTION:In a PGA 2, four lead pins 9a inserted into a through-hole 8 positioned at four corners of a substrate 3 are longer than remaining lead pins 9. While ends of the remaining lead pins 9 are in contact with the surface of a land 10, the four lead pins 9a are inserted inside four holes 12 provided to a packaging substrate 1 and each end is projected slightly outside from the rear. That is, solder paste is applied to the surface of the land 10, the PGA 2 is laminated on the upper surface of the packaging substrate 1, and the lead pin 9a is inserted inside the hole 12 of the packaging substrate 1; thereby, an end of each of remaining lead pins 9 is temporarily fixed, which is positioned accurately on the surface of each opposite land 10. Thereby, it is possible to prevent misregistration of the PGA 2 readily and surely, which is surface- packaged on the packaging substrate 1.

7. 发明专利

JPH03173152A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03173152A
公开(公告)日：1991-07-26
申请号：JP31063889
申请日：1989-12-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： AKASAKI HIROSHI , OTSUKA KANJI
IPC分类号： H01L23/02
摘要： PURPOSE:To prevent a retreat of a bonding member and a blowhole from being produced at a sealing part by a method wherein a thickness and a volume of the bonding member at the sealing part and a heat-conducting part are adjusted, a pressure is self-adjusted in such a way that a pressure inside a cavity of a mounting board becomes equal to a pressure outside the cavity and the bonding member is sealed airtightly. CONSTITUTION:Solder preforms (bonding member preforms) 6a of a sealing part 5, a solder preform (a bonding member preform) 8a of a heat-conducting part 7 and a cap 3 are aligned respectively with metallized layers 9, 10, 11 and are piled up on a mounting board 2 on which a semiconductor chip 1 has been mounted via solder bumps 4. In this case, a thickness of the solder preforms 6a of the sealing part 5 which have been formed as, e.g. square posts is set to a value close to a sealing thickness at a time when a sealing operation is completed. The solder preform 8a of the heat-conducting part 7 is set to a volume which becomes a prescribed solder thickness at the time when the sealing operation is completed. When an area of a plane part is reduced, the preform formed to be a square post which is thicker than the solder preforms 6a of the sealing part can be used while its volume is kept definite.

8. 发明专利

JPH02288232A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02288232A
公开(公告)日：1990-11-28
申请号：JP10767589
申请日：1989-04-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： AKASAKI HIROSHI , ISHIDA TAKASHI , TATE HIROSHI
IPC分类号： H01L21/3213 , H01L21/3205 , H01L21/321 , H01L21/60
摘要： PURPOSE:To shorten a manufacturing process by forming insulating protective films as a lower layer and an upper layer onto the metallic wiring layer of a flip-chip electrode section and an external exposed pad section and simultaneously conducting the etching process of the machining of the upper-layer insulating protective film with the flip-chip electrode section and the external exposed pad section. CONSTITUTION:An SiO2 film 7 as an upper-layer insulating protective film is shaped onto the surfaces of an opened flip-chip electrode section 2 and an external exposed pad section 3. The SiO2 film 7 of the flip-chip electrode section 2 and the external exposed pad section 3 is opened through wet etching by a hydrofluoric acid group etchant. Since the etching rates of the SiO2 film 7 of the upper-layer insulating protective film and the Si3N4 film 6 of a lower-layer insulating protective film differ and the etching rate of the Si3N4 film 6 is made lower than that of the SiO2 film 7 by approximately centuple at that time, the etching of the external exposed pad section 3 progresses only up to the surface of the lower-layer insulating film, and the Si3N4 film 6 is not etched. Since the SiO2 film 7 formed to the flip-chip electrode section 2 and the external exposed pad section 3 can be opened simultaneously through wet etching, the upper-layer insulating protective film can be machined at a time.

9. 发明专利

JPH02144938A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02144938A
公开(公告)日：1990-06-04
申请号：JP29812788
申请日：1988-11-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , OTSUKA KANJI , AKASAKI HIROSHI , EMATA KOJI , KIKUCHI NORISHIGE
IPC分类号： H01L23/522 , H01L21/768
摘要： PURPOSE:To narrow a pitch between wiring parts and to realize a high integra tion by a method wherein a first wiring group and a second wiring group are laminated and connected at the bottom of a groove extended and installed breadthwise on a wiring part constituting the wiring groups on a substrate. CONSTITUTION:An insulating film 3a composed of a polyimide or the like is formed on the surface of a package substrate 2 composed of a ceramic material. A plurality of first-layer wiring parts 4 constituting a first wiring group are extended and installed nearly in parallel; an interlayer insulating film 3b composed of the polyimide or the like is formed so as to cover a plurality of the first-layer wiring parts 4. A plurality of second-layer wiring parts 5 constituting a second wiring group are extended and installed nearly in parallel; a plurality of second-layer wiring parts 5 are laminated individually on and connected electrically to plurality of the first-layer wiring parts 4 at the bottom of one through hole (a groove) 6a formed in the interlayer insulating film 3b.

10. 发明专利

JPH01286453A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01286453A
公开(公告)日：1989-11-17
申请号：JP11466888
申请日：1988-05-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： EMATA KOJI , OKINAGA TAKAYUKI , SHIRAI MASAYUKI , OTSUKA KANJI , AKASAKI HIROSHI
IPC分类号： H01L23/10 , H01L23/24 , H01L23/28
摘要： PURPOSE:To improve the throughput in a manufacturing line, and enable the cost reduction by forming a dam to be arranged on the upper surface of a base, by using adhesive agent. CONSTITUTION:On a dam forming part on the periphery of a semiconductor chip 12 in the central part of the upper surface of a base 11, an adhesive agent like silicon rubber having high viscosity is spread so as to be higher than the upper surface of a semiconductor chip 12. In a region surrounded by said silicon rubber or the like, coating material 17 like silicon gel or the like is subjected to potting so as to completely cover the semiconductor chip 12 and an aluminum wire 15. The adhesive agent and the coating material 17 are hardened at the same time by baking. After that adhesive agent like silicon rubber is spread on the fixing part of a cap 18, and fixed by performing baking while pressure is applied to the cap 18. The cap is provided with a recessed part so as to hide the tops 19 of lead pins 14.

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