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1. 发明专利

JP2001078057A NOISE REDUCTION SIGNAL PROCESSOR 失效
公开(公告)号：JP2001078057A
公开(公告)日：2001-03-23
申请号：JP24984899
申请日：1999-09-03
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： KIMURA KATSUNOBU , MATONO TAKAAKI , TAKADA HARUKI , NAGATA TATSUO , SUGIYAMA MASAHITO , TSURU YASUTAKA , SUDO KOICHI
IPC分类号： H04N5/213 , H03M1/12
摘要： PROBLEM TO BE SOLVED: To optimally perform noise reduction irrespective of the contents of an image by outputting a noise reduction signal from a noise cancel polarity signal and minimum value data and outputting a video signal, to which noise reducing processing is applied, from an input video signal and the noise reduction signal. SOLUTION: A minimum value detecting circuit 70 is provided with a minimum value data output function for inputting a limit value inputted from the outside and corrected and a differential signal, outputting this corrected limit value when this corrected limit value exceeds the value of the differential signal and outputting the differential signal as minimum value data when the differential signal is smaller than the corrected limit value. A differential quantity adaptive control circuit 80 and an addition/subtraction selector circuit 30 are provided with a noise reduction signal generating function for outputting the noise reduction signal from the noise cancel polarity signal and the minimum value data and a noise reduction processed video signal output function for outputting the video signal, to which noise reducing processing is applied, from the input video signal and the noise reduction signal.

2. 发明专利

JPH11355610A CONTOUR CORRECTION CIRCUIT 失效
公开(公告)号：JPH11355610A
公开(公告)日：1999-12-24
申请号：JP15460298
申请日：1998-06-03
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： NAGATA TATSUO , TAKADA HARUKI , KIMURA KATSUNOBU , SUDO KOICHI , MATONO TAKAAKI
IPC分类号： H04N5/208
摘要： PROBLEM TO BE SOLVED: To prevent a framing phenomenon from being generated at the contour part of television and personal computer video images. SOLUTION: This circuit is provided with an HPF 102 for extracting high band components corresponding to the contour part of video signals and the polarity signals, a difference detection circuit 103 for detecting a maximum value and a minimum value in an object video image area, a clip level generation circuit 104 for performing the addition of an offset value set beforehand and replacement with an amplitude level to the maximum value and the minimum value and deciding a clip level, a maximum/minimum selection circuit 106 for clipping high band signals at the clip level and an adder 107 for adding the output of the maximum/minimum selection circuit 106 to the video signals from the difference detection circuit.

3. 发明专利

JPH0678237A TELEVISION SIGNAL RECEIVER 失效
公开(公告)号：JPH0678237A
公开(公告)日：1994-03-18
申请号：JP22903192
申请日：1992-08-28
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MATONO TAKAAKI , SAKAI TAKESHI , UENO AKIRA , KUBOTA SADAO
IPC分类号： H04N5/46 , H04N7/01
摘要： PURPOSE:To decrease power consumption and to decrease interference by the high frequency of a clock signal to a TV tuner in a receiver which incorporates a MUSE decoder and a MUSE-NTSC conversion circuit, etc., by providing a relay circuit by which the power source of a MUSE-NTSC discrimination circuit and that of the MUSE decoder or the MUSE-NTSC conversion circuit are turned on/off. CONSTITUTION:When a signal currently received shows a MUSE signal, a system microcomputer 123 controls signal switching circuits 113, 114, and outputs the output signal of the MUSE-NTSC conversion circuit 112 to an EDTV signal processing part 115, and makes the part output it to a display device 119. At this time, the MUSE-NTSC discrimination circuit 127 turns on the relay circuit 121, and supplies power from a power source circuit 122 to the MUSE-NTSC conversion circuit 112. When the signal being received is not the MUSE signal, the MUSE-NTSC discrimination circuit 127 turns off the relay circuit 121, and stops the supply of the power to the MUSE-NTSC conversion circuit 112.

4. 发明专利

JP2000138875A TELEVISION RECEIVER 失效
公开(公告)号：JP2000138875A
公开(公告)日：2000-05-16
申请号：JP33093499
申请日：1999-11-22
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： KATSUMATA KENJI , HIRAHATA SHIGERU , TAKADA HARUKI , KONNO MITSUHISA , ISHIBASHI KOICHI , KAIZAKI KAZUHIRO , MATONO TAKAAKI , HARATANI ATSUSHI
IPC分类号： H04N5/44 , H04N7/01
摘要： PROBLEM TO BE SOLVED: To magnify a video image according to a plurality of magnifications by allowing a magnification control means to conduct read stop control for a storage means, and synchronously outputs a coefficient used for filter processing of a spatial filter processing to the spatial filter means. SOLUTION: A magnification control means conducts read-stop control for a storage means, and synchronously outputs a coefficient used for filter processing of a spatial filter processing to the spatial filter means. In this television receiver, while the gate signal of a read clock is turned off, the read clock of a memory is stopped and read of one inter-line data is stopped. For example, when magnifying at a multiple of 4/3, a vertical magnification control circuit 204 gives a control signal to turned off a read gate to a 1st memory circuit 104 by a period, i.e., once every 4 lines. Thus, the 1st memory circuit 104 decides on the magnified position and a period for scanning magnification and outputs a prescribed signal.

5. 发明专利

JPH05252457A 失效
公开(公告)号：JPH05252457A
公开(公告)日：1993-09-28
申请号：JP24729291
申请日：1991-09-26
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： KATSUMATA KENJI , HIRAHATA SHIGERU , TAKADA HARUKI , KONNO MITSUHISA , ISHIBASHI KOICHI , KAIZAKI KAZUHIRO , MATONO TAKAAKI , HARATANI ATSUSHI
IPC分类号： G06T3/40 , H04N5/262 , H04N5/44 , H04N7/01
摘要： PURPOSE:To suppress a jitter component by enlarging a standard TV signal to arbitrary size in accordance with its feature and displaying it in optimal size on a display having a specific aspect ratio. CONSTITUTION:A video signal of progressive scanning inputted from an input terminal 101 is enlarged in the vertical direction, and the horizontal direction by a first memory 104, and a second memory circuit 105, respectively. In this case, a synchronization processing circuit 108 is provided with the circuits 104, 105 which supply a clock to each circuit, and can read out intermittently a write clock by a high clock of >=4/3. In such a state, a space filter 106 controls the circuit 105, and enlarges the input video signal to arbitrary size. As a result, on a display device having an aspect ratio of 16:9, various kinds of softwares such as a signal of movie size, etc., can be displayed by converting them to signals of suitable size, respectively. The enlarged signal becomes a video signal which scarcely generates a jitter and can be displayed on a prescribed display.

6. 发明专利

JP2003134476A SCAN CONVERSION PROCESSOR 审中-公开
公开(公告)号：JP2003134476A
公开(公告)日：2003-05-09
申请号：JP2001325765
申请日：2001-10-24
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MIZUHASHI YOSHIAKI , NAKAJIMA MITSUO , TSURU YASUTAKA , OGINO MASAHIRO , MATSUKAWA MASAAKI , ISHIKURA KAZUO , MATONO TAKAAKI
IPC分类号： H04N19/50 , G09G5/00 , G09G5/391 , H04N7/01 , H04N19/105 , H04N19/132 , H04N19/139 , H04N19/159 , H04N19/176 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/503 , H04N19/513 , H04N19/577 , H04N19/85 , H04N7/32
摘要： PROBLEM TO BE SOLVED: To provide a motion compensation type scan conversion processing with reduced operation quantity when a stream signal in which interlace video is encoded by means of video coding processing obtained by combining a motion compensation predictive coding with orthogonal transformation coding. SOLUTION: This motion compensation type scan conversion processing contains decoding processing that inputs a steam signal subjected to video encoding obtained by combining motion compensation predictive coding and orthogonal transformation coding, decodes the stream signal and outputs an interlace video signal, motion vector information and control information, a motion vector conversion processing that generates a compensation vector converted into one inter-field from the motion vector information and the control information outputted from the decoding processing, and processing that inputs the interlace video signal, the control information and a compensation vector and outputs a sequential scanned image.

7. 发明专利

JP2003032636A Main scanning conversion equipment using movement compensation and main scanning conversion method 审中-公开
标题翻译：使用移动补偿和主扫描转换方法的主扫描转换设备
公开(公告)号：JP2003032636A
公开(公告)日：2003-01-31
申请号：JP2001217808
申请日：2001-07-18
申请人： Hitachi Ltd , Hitachi Video & Inf Syst Inc , 株式会社日立画像情報システム , 株式会社日立製作所
发明人： MIZUHASHI YOSHIAKI , NAKAJIMA MITSUO , TSURU YASUTAKA , OGINO MASAHIRO , ISHIKURA KAZUTO , MATSUKAWA MASAAKI , KATO WATARU , MATONO TAKAAKI
IPC分类号： H04N7/01
摘要： PROBLEM TO BE SOLVED: To realize main scanning conversion of high image quality wherein deterioration of image is restrained when a movement vector different from actual movement is detected in movement compensation type scanning conversion.
SOLUTION: This main scanning conversion equipment 1 for converting an interlace signal to a sequential scanning image signal is provided with an interpolation part 3 for a still image which produces an interpolation signal between fields, an interpolation part 2 for a moving image which produces an interpolation signal in a field, a movement vector detecting part 4 for detecting a movement vector, a reinforcement signal producing part 5 for producing a reinforcement signal, a reinforcement signal adding part 6 which produces a reinforced interpolation signal in a field by adding the reinforcement signal to the interpolation signal in a field, a movement detecting part 7 for detecting moving amount, a movement adaptation adding part 8 which produces a movement adapting interpolation signal by switching over an adding ratio between the interpolation signal in a field and the interpolation signal between fields in accordance with the moving amount, and double-speed process part 9 which performs time axis compression and time series alignment change of the interlace signal and the movement adapting interpolation signal.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了实现在移动补偿型扫描转换中检测到与实际移动不同的运动矢量时抑制图像劣化的高图像质量的主扫描转换。解决方案：将用于将交错信号转换为顺序扫描图像信号的主扫描转换设备1设置有用于在场之间产生插值信号的静止图像的内插部分3，用于产生插值的运动图像的插值部分2 信号，用于检测运动矢量的运动矢量检测部分4，用于产生加强信号的加强信号产生部分5，加强信号增加部分6，其通过将加强信号加到场中产生加强插补信号场中的内插信号，用于检测移动量的移动检测部7，移动适应加法部8，其通过切换场中的内插信号与场之间的插补信号之间的相加比来产生移动适应插值信号按照移动量，双速加工第9部分对交错信号和运动适应插值信号进行时间轴压缩和时间序列对准改变。

8. 发明专利

JP2000221930A IMAGE DISPLAY DEVICE AND IMAGE DISPLAY METHOD 失效
公开(公告)号：JP2000221930A
公开(公告)日：2000-08-11
申请号：JP2405299
申请日：1999-02-01
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： SOMEYA RYUICHI , KATO WATARU , SUGIYAMA MASAHITO , MATONO TAKAAKI , HASEGAWA AKIRA , SUZUKI AKIHIRO
IPC分类号： G09G3/36 , G09G3/20
摘要： PROBLEM TO BE SOLVED: To realize an image display device and a picture image, having no flicker and an improved image quality, capable of calculating an optimum sampling timing of an image signal even in the case of a slowly-rising image signal, and an image display method. SOLUTION: The point of time t1 and the point of time t2 when a voltage level of one pixel signal waveform reaches 20% and 80% respectively are detected, and t1 is subtracted from t2, and the subtraction result is multiplied by a coefficient K, to thereby estimate a rising period t0-80 of the voltage level of an image signal from 0% to 80%. Then, the period t0-80 and a jitter portion toff of a sampling clock are subtracted from a known one pixel period tdot, to thereby calculate a period from the point of time when the voltage level of the image signal reaches 80% to the optimum sampling timing topt. Then, the image signal is sampled based on the calculated period.

9. 发明专利

JP2000078433A Pll circuit, ad conversion circuit using the same and video signal processor 审中-公开
标题翻译： PLL电路，使用其的AD转换电路和视频信号处理器
公开(公告)号：JP2000078433A
公开(公告)日：2000-03-14
申请号：JP24285998
申请日：1998-08-28
申请人： Hitachi Ltd , Hitachi Video & Inf Syst Inc , 株式会社日立画像情報システム , 株式会社日立製作所
发明人： KIMURA KATSUNOBU , MATONO TAKAAKI , SAKAI TAKESHI , SUGIYAMA MASAHITO , ISHIKURA KAZUO , SUDO KOICHI
IPC分类号： H04N5/06 , G09G5/00 , G09G5/18 , H03L7/081 , H03M1/00
摘要： PROBLEM TO BE SOLVED: To obtain a highly accurate PLL capable of variably adjusting the phase relation between a dot clock signal and an analog video signal without providing an expensive IC by outputting the dot clock signal by varying frequency according to a DC value of a loop filter output to output a voltage difference signal by filtering it and converting it into a DC signal.
SOLUTION: Frequency information of vertical and horizontal synchronizing signals of various video standards are stored in a microcomputer 120, the standard is judged and held by collating the frequency information of the video standard and the frequency information of the vertical and horizontal synchronizing signal to be inputted. And information on frequency division from the microcomputer 120 is stored in a frequency divider pulse generation circuit 110. On the other hand, the dot clock signal generated by a voltage control oscillator 119 is supplied to a clock input terminal of a counter like a counter of the frequency divider pulse generating circuit 110, the frequency is divided 1/n by the counter and an H pulse signal formed by dividing the frequency by 1/n is outputted from the frequency divider pulse generating circuit 110.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：为了获得能够通过根据循环的DC值通过改变频率输出点时钟信号而不提供昂贵的IC来可变化地调整点时钟信号和模拟视频信号之间的相位关系的高精度PLL 滤波器输出，通过对其进行滤波并将其转换为直流信号来输出电压差信号。解决方案：将各种视频标准的垂直和水平同步信号的频率信息存储在微型计算机120中，通过将视频标准的频率信息和要输入的垂直和水平同步信号的频率信息进行比较来判断和保持标准。并且来自微型计算机120的分频信息存储在分频脉冲发生电路110中。另一方面，由压控振荡器119产生的点时钟信号被提供给计数器的时钟输入端，像计数器的计数器分频器脉冲发生电路110，频率被计数器分频为1 / n，并且由分频器脉冲产生电路110输出由频率除以1 / n形成的H脉冲信号。

10. 发明专利

JPH07250309A MUSE DECODER 失效
公开(公告)号：JPH07250309A
公开(公告)日：1995-09-26
申请号：JP4162194
申请日：1994-03-14
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MIZUGUCHI TAKAHIRO , MATONO TAKAAKI , NAGATA TATSUO , MATSUKAWA MASAAKI
IPC分类号： H04N5/205 , H04N5/455 , H04N7/015 , H04N9/64
摘要： PURPOSE:To inhibit waveform equalization processing in a waveform equalization means while special reproduction is finished in a high definition video reproduction device and a MUSE signal is in an unstable state. CONSTITUTION:A waveform equalization circuit 104 applies waveform equalization to a MUSE signal from an A/D converter circuit 103. A sound frame synchronization detection circuit 109 detects a bit pattern of a sound frame synchronizing signal from digital sound data from a sound processing section 108 and provides an output of a waveform equalization control signal only when the bit pattern is not detected. A delay circuit 110 receives the waveform equalization control signal from the sound frame synchronization detection circuit 109 and delays the signal by a prescribed time and provides a resulting output. The prescribed delay time is selected to be a time till the MUSE signal reaches a stable state after special reproduction is finished. Upon the receipt of the waveform equalization control signal from the delay circuit 110, the waveform equalization circuit 104 stops the waveform equalization processing and restarts the waveform equalization processing when no waveform equalization control signal is received.

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