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1. 发明专利

JP2002311826A ENCODING AND DECODING DEVICE, METHOD FOR ENCODING AND DECODING, DATA ENCIPHERING METHOD AND IC CARD 失效
公开(公告)号：JP2002311826A
公开(公告)日：2002-10-25
申请号：JP2001116254
申请日：2001-04-16
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TAKAHASHI MASAAKI
IPC分类号： G06K19/00 , G06K19/07 , G09C1/00 , H03M7/30 , H04L9/06 , H04L9/10
摘要： PROBLEM TO BE SOLVED: To provide an encoding and decoding device and encoding and decoding methods which enable stable intensification of security protection with a simple configuration and to provide an IC card. SOLUTION: One of non-inversion data corresponding to normal sentence data or processing unit data of an enciphered sentence or inversion data of the whole bits are fetched at random and, then, the data is inverted and ciphered in response to non-inversion data in a positive scrambling signal processing. The positive scrambling signal processing is performed in parallel with a negative scrambling signal processing for inverting and enciphering corresponding to the inversion data. One of output signals corresponding to the respective processings is taken-out in accordance with a data selecting operation in the first signal processing and the taking-out processing is repeated a plurality of times. Then the final result of inversion and ciphering is adopted as encoding data or decoding data.

2. 发明专利

JP2001266103A IC CARD AND MICROCOMPUTER 失效
公开(公告)号：JP2001266103A
公开(公告)日：2001-09-28
申请号：JP2000323178
申请日：2000-10-23
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANIMOTO CHIAKI , NAKADA KUNIHIKO , NARIYOSHI YUICHIRO , TSUKAMOTO TAKU , HIRABAYASHI SHIGEO , WATASE HIROSHI , TAKAHASHI MASAAKI
IPC分类号： G06K19/073 , G06F9/30 , G06F9/38 , G06F15/78 , G06F21/06 , G09C1/00
摘要： PROBLEM TO BE SOLVED: To provide an IC card and a microcomputer, which reinforce security and speed up and reinforce a signal processing for security. SOLUTION: In an IC card, an operation voltage is supplied by the electrical connection of an outer terminal with a read/write device and the input/output operation of data with a ciphering processing and a decoding processing is performed. A dummy processing operation aiming at disturbance is included in the ciphering processing or the decoding processing and the operation timing and the operation current of an inner circuit are unified. In the microcomputer of module constitution, which includes the input/output operation of data with the ciphering processing or the decoding processing, the dummy processing operation aiming at disturbance is included in the ciphering processing or the decoding processing and the operation timing and the operation current of the inner circuit are unified.

3. 发明专利

JP2000259799A IC CARD AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000259799A
公开(公告)日：2000-09-22
申请号：JP6156199
申请日：1999-03-09
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： WATASE HIROSHI , NAGASAKI NOBUTAKA , TSUKAMOTO TAKU , TAIRA SATOSHI , TAKAHASHI MASAAKI , NAKADA KUNIHIKO , TERAUCHI CHIAKI , OKI MASARU , KAMINAGA MASAHIRO
IPC分类号： G06K19/07 , G06F12/14 , G06F15/78 , G09C1/00 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To provide an IC card and a semiconductor integrated circuit device realizing the enhancement of security. SOLUTION: In the IC card or semiconductor integrated circuit device which includes a data processor and a ROM where data processing procedures including security information processing by such a data processor are written and to which an operation voltage is applied by such a manner that an external terminal is electrically connected to an external device such as a reader-writer and in which a data processing operation following the data processing procedures is performed, the security is obtained by making it substantially impossible to perform data dependence analysis such as to compare a current waveform on the time base because the procedure and timing for cipher processing change every time and a consumption current waveform in the case of being seen from a time base change by providing a means that makes the timing of the data processing procedures change.

4. 发明专利

JP2001092516A NUMERICALLY CONTROLLED CURVED SURFACE WORKING DEVICE 失效
公开(公告)号：JP2001092516A
公开(公告)日：2001-04-06
申请号：JP26504299
申请日：1999-09-20
申请人： HITACHI LTD , HITACHI SOFTWARE ENG
发明人： HIRAI JUNICHI , ARAI HIROSHI , HARIHARA TAMOTSU , CHIBA OSAMU , TAKAHASHI MASAAKI
IPC分类号： G05B19/4103 , B23Q15/00 , G05B19/4099
摘要： PROBLEM TO BE SOLVED: To provide a numerically controlled curved surface working device capable of improving the roughness of a working surface and the accuracy of the working surface by smoothly moving and working a tool along an NURBS curve, executing a high speed working and sharply shortening the working manhour by omitting manual work. SOLUTION: This working device is provided with a means for reading out CL data consisting of a tool tip position vector and a main axis direction vector in a work coordinate system, a means for converting the CL data into the positional vectors and rotational angles of three straight axes in a machine coordinate system on the basis of the constitution of a simultaneous multi-axes controlling NC working machine, a means for calculating a not vector of an optimum interval for a NURBS curve on the basis of the positional vectors and the rotational angles of the three straight axes, and a means for calculating NURBS curves for the three straight axes and a rotational axis on the basis of the not vector. The device is also provided with a means for converting the NURBS curves into NC data for interpolating NURBS, a means for converting the working speed of the work coordinate system into a minute feed working speed of the machine coordinate system and a means for transmitting the NC data to an NC working machine to execute an NURBS interpolated work.

5. 发明专利

JPH1117071A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH1117071A
公开(公告)日：1999-01-22
申请号：JP16561597
申请日：1997-06-23
申请人： HITACHI LTD
发明人： OGAWA TOSHIO , TAKAHASHI MASAAKI , AIDA MASAHIRO , KAMIMURA NORITAKA , SUZUKI KAZUHIRO
IPC分类号： H01L23/29 , H01L23/31
摘要： PROBLEM TO BE SOLVED: To suppress the warp of a molded product and minimize the internal stress due to mounting on a heat sink to realize a high reliability and ensure a low thermal resistance, by specifying the linear expansion coefficient ratio of a metal board to a resin mold. SOLUTION: A device has a power semiconductor element 11 fixed to a lead frame 13 through a solder layer. The lead frame 13 is adhered to a metal board 19 through an insulation layer 18, the element 11 is electrically bonded by an Al wire bonding part 16 and molded with an armor resin mold 17 to form an integrated structure, and the linear thermal expansion coefficient of the resin mold 17 is adjusted relative to that of the board 11 in a ratio of 0.3:1-0.6:1 in the actual temp. range. Thus, the warp of the molded product is suppressed, and hence the internal stress due to mounting on a heat sink, etc., is minimized.

6. 发明专利

JPH10125826A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH10125826A
公开(公告)日：1998-05-15
申请号：JP28205496
申请日：1996-10-24
申请人： HITACHI LTD
发明人： TAKAHASHI MASAAKI , OGAWA TOSHIO , AIDA MASAHIRO , KAMIMURA NORITAKA , SUZUKI KAZUHIRO , ENDO TSUNEHIRO
IPC分类号： H01L23/28 , H01L23/29 , H01L25/07 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To avoid causing a poor dielectric strength or increasing the thermal resistance by joining a heat sink to a lead frame through an org. resin-made insulation adhesive sheet. SOLUTION: On a lead frame 2 semiconductor chips 4 or electronic components such as resistors and capacitors are mounted and molded with a thermosetting resin. Thus formed semiconductor device comprises a heat sink 1 and lead frame 2 adhered each other through an org. resin-made insulation adhesive sheet 7 and hermetically sealed with a thermosetting resin. The lead frame 2 with a semiconductor chip 4 bonded thereto, adhesive sheet 7 and metal base or metal heat sink 1 are laminated and provisionally adhered. This sample is set in a die 8 to press and seal it with a molding resin. The adhesive sheet 7 contains an inorg. component e.g. alumina 60-95wt.% in the thermosetting resin.

7. 发明专利

JPH1093015A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH1093015A
公开(公告)日：1998-04-10
申请号：JP24013296
申请日：1996-09-11
申请人： HITACHI LTD
发明人： OGAWA TOSHIO , TAKAHASHI MASAAKI , AIDA MASAHIRO , KAMIMURA NORITAKA , YAMADA KAZUJI , SUZUKI KAZUHIRO , ENDO TSUNEHIRO , SHIGEMURA TATSUYA , NAKATSU KINYA
IPC分类号： H01L25/07 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To relax the stress concn. on an insulation layer, when the temp. changes by providing a heat sink held between electric insulation layers on the lead frame bottom face and forming a resin mold integrated with them, to form a uniform stable thickness insulation layer. SOLUTION: A high thermal conductivity type heat diffusion board 19, e.g. is fixed to a power semiconductor element 11 via 9 solder 12, etc. The element 11 is fixed to a Cu lead frame 13 through a second solder layer 12. The lead frame 13 has been previously fixed to a Cu heat sink 15 by a resin insulation layer 18. The semiconductor element 11 is electrically connected to a wiring layer by bonding wires 16, and the entire system is formed by an armor resin mold 17 in a single body. Thus it is possible to disposes a homogeneous and flat insulating layer on a metal plate surface and relax the stress concn. on the insulation layer 18, when the temp. changes since the entire circuit is covered with the single-mold resin layer.

8. 发明专利

JPH08191120A POWER SEMICONDUCTOR ELEMENT SUBSTRATE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08191120A
公开(公告)日：1996-07-23
申请号：JP206695
申请日：1995-01-10
申请人： HITACHI LTD
发明人： OGAWA TOSHIO , TAKAHASHI MASAAKI , KAMIMURA NORITAKA , YAMADA KAZUJI
IPC分类号： H05K1/02 , H01L23/12 , H01L23/373 , H01L23/473
摘要： PURPOSE: To obtain a power semiconductor element substrate, which inhibits thermal strain of ceramic chips while ensuring a high heat conductivity between the ceramic chips and a metal heat sink and makes the adhesion between both of the chips and the heat sink superior, by a method wherein AIN chips are buried in an Al/SiC base in such a way that the exposed surfaces of the AIN chips are on the same plane as the exposed surface of the base. CONSTITUTION: A power semiconductor element substrate is manufactured into such a structure that AIN chips 12 are buried in a base 13, which contains Al and SiC as its main component, by an injection molding method and the exposed surfaces (free surfaces) 12A of the chips 12 are on the same plane as the exposed surface 13A of the base 13. Power semiconductor elements 11 may be directly bonded to the surfaces of the chips 12, but are secured to the chips 12 via lower electrodes 17 as needed. In this case, a bridge-shaped electrode 18 is designed so that it is connected with the electrodes 17 of the elements 11 adjacent to the electrode 18 and ensures a current value requied for the several elements in all. As a result, the temperature rise of the power semiconductor elements is inhibited and a heat dissipation burden, which is applied to a heat sink, can be made small.

9. 发明专利

JPH0682831B2 失效
公开(公告)号：JPH0682831B2
公开(公告)日：1994-10-19
申请号：JP7840085
申请日：1985-04-15
申请人： HITACHI LTD
发明人： TAKAHASHI MASAAKI , MURAKAMI SUSUMU , KAGAMI TERUYUKI
IPC分类号： H01L29/06 , H01L29/40 , H01L29/74

10. 发明专利

JPH05175353A SEMICONDUCTOR CHIP CARRIER AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH05175353A
公开(公告)日：1993-07-13
申请号：JP34271891
申请日：1991-12-25
申请人： HITACHI LTD
发明人： TAKAHASHI MASAAKI , ABE YOICHI , KATO AKIRA , OGIWARA SATORU , SHINOHARA KOICHI
IPC分类号： H01G4/33 , H01G4/06 , H01L21/768 , H01L21/822 , H01L23/12 , H01L25/00 , H01L27/04
摘要： PURPOSE:To reduce erroneous operations of a semiconductor device by coating polyimide resin, etc., on the surface of a ceramic chip carrier, flattening it, forming a dielectric film on the lower electrode surface through an oxide film, and then preventing diffusion of the electrode metal to the dielectric film by heat treatment. CONSTITUTION:A chip carrier has a through-hole conductor 2 in itself and the through-hole conductor 2 connects a semiconductor chip 1 to a module substrate 13. A flattening film 5 is formed on one surface of the chip carrier to flatten the ceramic surface and a matching layer 4 for compensating misalignment of the through-hole conductor 2 is formed. A capacitor for eliminating a power supply noise is constituted by forming an insulator 7 and a dielectric film 8 on a lower electrode 6 performing heat treatment, depositing an upper electrode 9 and then forming a protective film 10 on the surface. A through-hole conductor is located at one part of the insulator 7, the dielectric film 8, and the protective film 10 for making connection to the semiconductor chip.

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