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1. 发明专利

JP2000323568A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000323568A
公开(公告)日：2000-11-24
申请号：JP13000299
申请日：1999-05-11
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SATO AKIRA , MIYAZAKI HIROSHI , FUKADA SHINICHI , AOKI HIDEO , OSHIMA TAKAFUMI
IPC分类号： H01L21/768 , H01L21/28
摘要： PROBLEM TO BE SOLVED: To reduce the dishing or erosion by removing a barrier metal film in wiring layer trenches formed into an insulation film and vias at lower parts thereof, etc., except their side walls, etc. SOLUTION: Wiring layer trenches 18 and vias 19 are formed into an insulation film on a semiconductor substrate 1 and a TiN barrier metal film 20 is deposited. Using the etch back method, this film 20 is etched back to remove the barrier metal film 20 on lower parts of the vias 19 and the surface, etc., of the insulation film, thereby forming a pattern of the barrier metal film 20 for side walls only in the trenches 18 and on the side walls of the vias 19 at the lower parts thereof. Wiring metal layers 21, 22 composed of Cu layers for seed layers are formed on a semiconductor substrate 1. This extremely reduces dishing and erosion and a high-performance and high-reliability semiconductor device can be manufactured.

2. 发明专利

JPH11191298A NON-VOLATILE SEMICONDUCTOR STORAGE 失效
公开(公告)号：JPH11191298A
公开(公告)日：1999-07-13
申请号：JP35925897
申请日：1997-12-26
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANAKA TOSHIHIRO , SHINAGAWA YUTAKA , SHIBA KAZUYOSHI , SUZUKAWA KAZUFUMI , FUJITO MASAMICHI , OSHIMA TAKAFUMI , ABE SONOKO , MATSUBARA KIYOSHI
IPC分类号： G11C16/04 , G11C16/06 , G11C16/24 , G11C16/30 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a memory cell connecting system in which parasitic capacity of a bit line can be reduced by technology in which connection of memory cells constituting a memory array is hierarchical constitution of a sub-bit line and read-out operation speed can be increased, and a taking method for differential input of a differential type sense amplifier. SOLUTION: This device is provided with Sid-MOS connecting a main bit line BL and a sub-bit line as a memory cell connecting system and transistor Sid-MOS discharging the sub-bit line. In read-out operation, a gate signal SiDB is a complementary signal of a gate signal Sid of Sid-MOS. Precharge of a read-out bit line and a reference bit line is performed before selecting Sid-MOS using a differential type sense amplifier. Further, this device is provided with a function by which an approximately half current of a memory cell is made to flow to a read-out bit line in the direction of canceling a memory cell current.

3. 发明专利

JPH11185494A SEMICONDUCTOR STORAGE AND DATA PROCESSOR 失效
公开(公告)号：JPH11185494A
公开(公告)日：1999-07-09
申请号：JP35461397
申请日：1997-12-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI , FUJITO MASAMICHI , TANAKA TOSHIHIRO , OSHIMA TAKAFUMI
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To quicken read even in the case of relief. SOLUTION: A redundant block (SPA) for relieving a memory block containing a defect, a relief information holding means (REG) for holding relieve information, and selection means (WSEL and RSEL) for selecting the redundant block instead of the memory block with the defect based on the held information of the relief information holding means for circuit operation are provided. They select the redundant block instead of the memory cell array with the defect for circuit operation, thus eliminating the need to compare an input address with a redundant one for each input of an address signal and hence quickening memory access.

4. 发明专利

JPH11186527A LATCH CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING DEVICE 失效
公开(公告)号：JPH11186527A
公开(公告)日：1999-07-09
申请号：JP35461697
申请日：1997-12-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： FUJITO MASAMICHI , SUZUKAWA KAZUFUMI , MISHINA DAISUKE , KAWAI YOZO , SHINAGAWA YUTAKA , TANAKA TOSHIHIRO , OSHIMA TAKAFUMI
IPC分类号： G11C16/02 , H01L21/8247 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To stabilize latch operation. SOLUTION: A latch control circuit consists of a transfer MOS (62) of an n-channel MOS transistor and a latch circuit (DBL) which latches data which are transmitted from a logic circuit disposed in a stage before the transfer MOS 62 via the transfer MOS. In this case, when data is taken to the latch circuit via the transfer MOS 62, the power source voltage (VCCW) on the high potential side of the latch circuit (DBL) is set lower than that of the logic circuit to stabilize the latch operation, without increasing the layout area of the latch circuit, and the externally supplied voltage can be lowered.

5. 发明专利

JP2012080133A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2012080133A
公开(公告)日：2012-04-19
申请号：JP2012010607
申请日：2012-01-23
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NOGUCHI JUNJI , MATSUMOTO TAKASHI , OSHIMA TAKAFUMI , ONOZUKA TOSHIHIKO
IPC分类号： H01L23/522 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of reducing capacitance between wiring lines of a semiconductor device, and implementing a countermeasure against misalignment vias.SOLUTION: The manufacturing method of a semiconductor device comprises processes of: forming insulator films 74 in space areas on wiring lines and between wiring lines; removing the insulator films 74 in regions other than the peripheral regions of through holes which expose the top face of wiring lines whose intervals between adjacent wiring lines are narrow while leaving the insulator films 74 in the peripheral regions as reservoirs; and forming insulator films 77 on the wiring lines while leaving gaps in the space areas between the wiring lines where the insulator films 74 are removed.
摘要翻译：解决的问题：提供能够减小半导体器件的布线之间的电容的半导体器件的制造方法，并且实现针对不对准过孔的对策。解决方案：半导体器件的制造方法包括以下处理：在布线和布线之间的空间区域中形成绝缘膜74; 在绝缘膜74之外的区域中除去暴露出布线的顶面之外的区域中的绝缘膜74，其中相邻布线之间的间隔较窄，同时在外围区域中留下绝缘膜74作为储存器; 并且在布线上形成绝缘膜77，同时在除去绝缘膜74的布线之间的空间区留下间隙。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2011238771A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011238771A
公开(公告)日：2011-11-24
申请号：JP2010108904
申请日：2010-05-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYOSHI TOMOYUKI , WADA SHINICHIRO , OSHIMA TAKAFUMI , YANAGIDA YOHEI , FUJITA TAKAHIRO
IPC分类号： H01L29/861 , H01L29/78
CPC分类号： H01L29/7836 , H01L29/0692 , H01L29/8611
摘要： PROBLEM TO BE SOLVED: To provide a high breakdown voltage diode structure which has high reverse recovery capability and a high allowable forward current.SOLUTION: A distance d between an end in a longitudinal direction of a p-well layer 8 within an anode region and an element isolation region 10 formed so as to surround a diode is set to 5 μm or less, where a depletion layer extends to the element isolation region 10 when a maximum rating reverse voltage is applied. At the end of the p-well layer 8 during recovery in the reverse direction, the electric field intensity is reduced, a hole current is suppressed and the local temperature rise is suppressed.
摘要翻译：要解决的问题：提供具有高反向恢复能力和高允许正向电流的高击穿电压二极管结构。解决方案：在阳极区域内的p阱层8的纵向方向上的端部与形成为围绕二极管的元件隔离区域10之间的距离d设定为5μm以下，其中，当施加最大额定反向电压时，层延伸到元件隔离区域10。在反向恢复期间的p阱层8的端部，电场强度降低，空穴电流被抑制并且局部温度升高被抑制。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JPH1140775A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1140775A
公开(公告)日：1999-02-12
申请号：JP19697697
申请日：1997-07-23
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KAWAMOTO YOSHIFUMI , OJI YUZURU , YOSHIGAMI JIRO , KIMURA SHINICHIRO , YAMANAKA TOSHIAKI , OSHIMA TAKAFUMI , MURAKAMI HIDEKAZU
IPC分类号： H01L29/78 , H01L21/76 , H01L21/8234 , H01L21/8242 , H01L27/08 , H01L27/088 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To raise the degree of integration, by making the thickness of the gate insulating film corresponding to the border section with the gate electrode of a MOS transistor separated in trench type larger than the thickness of the gate insulating film corresponding to the border section with the gate electrode of the MOS transistor that the information processor has. SOLUTION: A semiconductor integrated circuit device has, as an information storage part 42, a DRAM cell having a MOS-type transistor separated in trench type, and is further equipped with an information processor 40 in addition. Then, the thickness of the gate insulating film 39 corresponding to the border section with the gate electrode of a diffusion layer, to serve as the source or the drain of the MOS transistor that the information processor 42 has, made larger than the thickness of the gate insulating film corresponding to the border section with the gate electrode of an impurity diffused layer, to serve as the source or drain of the MOS-type transistor that the information processor 40 has. As a result, high degree of integration by trench type separation can be secured.

8. 发明专利

JP2009290240A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009290240A
公开(公告)日：2009-12-10
申请号：JP2009207688
申请日：2009-09-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NOGUCHI JUNJI , MATSUMOTO TAKASHI , OSHIMA TAKAFUMI , ONOZUKA TOSHIHIKO
IPC分类号： H01L21/768 , H01L21/3205 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To efficiently attain capacity reduction and securement of a via processing margin. SOLUTION: This semiconductor device having a plurality of wiring layers has: a first wiring layer 26 having a predetermined region; a second wiring layer 47 located in an upper layer of the first wiring layer; an interlayer insulating film 36 provided between the first wiring layer and the second wiring layer; and barrier insulating films (29, 31) provided between the interlayer insulating film and wiring of the first wiring layer, wherein thickness of the barrier insulating film at an upper part of the wiring in the predetermined region is thicker than the barrier insulating film at an upper part of wiring in regions except the predetermined region, an air gap 35 is formed between the adjacent wirings in the predetermined region, and the air gap is not formed between the adjacent wirings in the regions except the predetermined region. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：有效地实现容量降低和通孔加工余量的确定。解决方案：具有多个布线层的该半导体器件具有：具有预定区域的第一布线层26; 位于第一布线层的上层的第二布线层47; 设置在第一布线层和第二布线层之间的层间绝缘膜36; 以及设置在所述层间绝缘膜和所述第一布线层的布线之间的阻挡绝缘膜（29,31），其中，所述预定区域中的所述布线的上部的所述阻挡绝缘膜的厚度比所述阻挡绝缘膜厚在预定区域以外的区域中布线的上部，在预定区域中的相邻布线之间形成气隙35，并且在除了预定区域之外的区域中的相邻布线之间不形成气隙。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2002033384A WIRING STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME 失效
公开(公告)号：JP2002033384A
公开(公告)日：2002-01-31
申请号：JP2000217215
申请日：2000-07-13
申请人： HITACHI LTD
发明人： HINODE KENJI , OSHIMA TAKAFUMI , TAKEDA KENICHI
IPC分类号： H01L23/522 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To provide drastic via wiring connection structure that has superior heat-resistance property, will not depend on the kinds of an insulating film, and can form a reliable wiring system and semiconductor device. SOLUTION: To make a via connected to wide wiring equivalent to connection for narrow wiring near a connection part, and the island of the insulating film is provided near the via in the wide wiring, and the width of wiring connected to the via is narrowed.

10. 发明专利

JP2011096862A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011096862A
公开(公告)日：2011-05-12
申请号：JP2009249673
申请日：2009-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYAMOTO YASUICHIRO , SHIMAMOTO SATOSHI , OSHIMA TAKAFUMI , WADA SHINICHIRO
IPC分类号： H01L27/088 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/092 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To reduce the manufacturing processes for a MOS transistor, and further prevent the threshold voltage of a parasitic MOS from being decreased.
SOLUTION: The method of manufacturing a semiconductor device eliminates ion implantation of impurities for channel formation on a field oxide film 30, in the method of ion implantation of impurities for channel formation of conductivity type reverse to that of a well diffusion layer after gate electrode formation. Accordingly, the semiconductor device has a structure wherein ion implantation of impurities for channel formation is not done to the field oxide film 30.
COPYRIGHT: (C)2011,JPO&INPIT

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