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1. 发明专利

JP2001236334A INTER-PROCESSOR COMMUNICATION METHOD AND PARALLEL PROCESSORS FOR SAME 失效
公开(公告)号：JP2001236334A
公开(公告)日：2001-08-31
申请号：JP2001004398
申请日：2001-01-12
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HAMANAKA NAOKI , NAKAKOSHI JUNJI , HIGUCHI TATSUO , CHIBA HIROYUKI , SHUDO SHINICHI , TAKEUCHI SHIGEO , OGATA YASUHIRO , TOBA TATSU
IPC分类号： G06F15/17 , G06F15/16
摘要： PROBLEM TO BE SOLVED: To decrease the overhead of a data copy for buffering by an OS when data are sent out to a network for inter-process communication. SOLUTION: A PATH table for finding a cluster number and the page table origin of another processes from a virtual communication path (PATH) from a process to another process is provided in an area for an OS in a memory corresponding to the processes. When data are transmitted, a cluster number and a page table origin are found by the PATH table from PATH specified by a transmission instruction and to the cluster specified by the former, the value and virtual address of the latter and data read directly out of the area of the process are transmitted. A reception-side cluster converts the virtual address and stores the data directly in the process area.

2. 发明专利

JP2002111774A PROCESSOR AND PARALLEL PROCESSING SYSTEM 失效
公开(公告)号：JP2002111774A
公开(公告)日：2002-04-12
申请号：JP2000301585
申请日：2000-10-02
申请人： HITACHI LTD
发明人： NAKAKOSHI JUNJI , SUZUKI ATSUHIRO , KAWAMURA TOSHIO
IPC分类号： G06F15/177 , G06F12/00 , H04L12/28 , H04L12/70 , H04L29/02 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To make it possible to generate a transmission demand during of transmission in a processor of transmission and receiving operation of a packet. SOLUTION: A transmission start register 131 for setting an address of a transfer control word block(TCWB) 160 as a transmission demand, a transmission state register 134 for indicating the state during transmission process in a transmission circuit, and a queue register 132 for joining a new TCWB to the TCWB during the transmission process are provided. When a new transmission demand is generated during indication of transmission process of the transmission state register 134, a command processor 107 sets a TCWB address for the new transmission demand in the queue register 132. A transmission circuit 103 refers to the queue register 132 after the transmission process is completed on the basis of the TCWB. When the TCWB address is set, the TCWB address is set to the transmission start register 131 and the transmission process is carried out continuously.

3. 发明专利

JP2001202345A PARALLEL PROCESSOR 失效
公开(公告)号：JP2001202345A
公开(公告)日：2001-07-27
申请号：JP2000017738
申请日：2000-01-21
申请人： HITACHI LTD
发明人： NAKAKOSHI JUNJI , SUZUKI ATSUHIRO
IPC分类号： G06F15/177 , G06F15/163 , G06F15/17 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To solve a problem it can not be confirmed whether each of divided packets is normally received or not for each packet when transferring transfer data on a network while dividing them into plural packets. SOLUTION: Transmitting data are divided into arbitrary packet size without overhead of software and generated into packet for the unit of a divided transmitting data length. Information capable of confirming whether the packet is normally received or not each time receiving this packet is transmitted while being applied to the header of each of packets.

4. 发明专利

JPH08161277A PARALLEL COMPUTER SYSTEM 失效
公开(公告)号：JPH08161277A
公开(公告)日：1996-06-21
申请号：JP33185794
申请日：1994-12-09
申请人： HITACHI LTD
发明人： WAKABAYASHI TORU , NAKAKOSHI JUNJI , ISOBE TADAAKI
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE: To improve the network connecting plural processors and performing an inter-processor data transfer, in a parallel computer system. CONSTITUTION: Each of plural processors 201 and 202 is provided with transmission circuit and reception circuit. A service processor 101 outputs a transmission permission signal and a reception permission signal to the transmission circuit and the reception circuit, respectively, outputs the network validating signal corresponding to each network to the both of the circuits and enables the inter- processor data transfer by the both networks. When a fault occurs in one network, the network validating signal of a faulty network is turned off, the transmission and reception permission signals are turned on and the inter-processor data transfer by other network is enabled, after the transmission and permission signals are turned off, the data transmission and reception are suppressed and all the data on the network is destroyed.

5. 发明专利

JPH06282511A FAULT PROCESSING DEVICE OF COMPUTER SYSTEM HAVING NETWORK 失效
公开(公告)号：JPH06282511A
公开(公告)日：1994-10-07
申请号：JP33053193
申请日：1993-12-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKEUCHI SHIGEO , INAGAMI YASUHIRO , NAKAKOSHI JUNJI , SHUDO SHINICHI , HIGUCHI TATSUO , FUJII KEIMEI , YASUDA YOSHIKO , OBARA KIYOHIRO , TOBA TATSU , YAMADA MASAHIRO
IPC分类号： G06F11/00 , G06F13/00 , G06F15/16 , G06F15/177
摘要： PURPOSE:To provide a network which does not affect on other message transfer even if any fault occurs in the process of a message transfer. CONSTITUTION:The fault detected by a fault detector 102 is held in a fault holding register A 110 or a fault holding register B 111, and the detected word number is held in a fault word number holding register 112. When a message generation circuit 120 judges that they are inputted and the fault is detected by a transfer destination processor number, the circuit 120 outputs a message to the processor shown by the transfer destination processor number at the time of the occurrence of the fault to be delivered from a selector 109. Because the message is made to be transferred to a proper processor in place of the transfer destination processor when a fault occurs in the transfer destination processor number of the message, the message does not stop in the network and does not affect on other message transfer.

6. 发明专利

JPH04332882A SCANNING CIRCUIT 失效
公开(公告)号：JPH04332882A
公开(公告)日：1992-11-19
申请号：JP10247591
申请日：1991-05-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKEUCHI SHIGEO , HAMANAKA NAOKI , NAKAKOSHI JUNJI , SATO YUJI , SHUDO SHINICHI , CHIBA HIROYUKI , HIGUCHI TATSUO , OGATA YASUHIRO , TOBA TATSU
IPC分类号： G01R31/28 , G06F11/22
摘要： PURPOSE:To enable a width of a scan data bus to be expanded and a time required for scan in/out to be reduced without increasing the number of pins of an LSI constituting a processing device for a data processing device with a scanning function. CONSTITUTION:A scanning circuit consists of selectors 15, 16, 18, and 19 and a scan-out data selection signal generation circuit 23. In the case of the scan- mode, D12 is selected and is output to DO0 and DO1. Also, in the case of scan- out operation of an LSI, either of D10 and D11 is selected by a signal 114 which is generated by the circuit 23 and then is output to the DO2 through selectors 16 and 17. A normal signal line and a scan data bus-are used commonly, thus enabling the width of the scan data bus to be expanded to a plurality of bits without increasing the number of pins in the LSI. Also, a tree structure with the scan data bus as a branch can be realized, thus enabling a relay LSI to be reduced.

7. 发明专利

JPH04326454A CROSS BUS NETWORK 失效
公开(公告)号：JPH04326454A
公开(公告)日：1992-11-16
申请号：JP9679191
申请日：1991-04-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： CHIBA HIROYUKI , SATO YUJI , NAKAKOSHI JUNJI , HAMANAKA NAOKI , SHUDO SHINICHI , HIGUCHI TATSUO , TAKEUCHI SHIGEO , OGATA YASUHIRO , TOBA TATSU
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80
摘要： PURPOSE:To average the data amount of an input buffer in a cross bus switch in a network for parallel computer, which is composed of cross bus switches. CONSTITUTION:FIFO 51, a waiting number counter 55, a threshold register 56, a comparator 57 and a request mask circuit 61 are given, and data whose number of waiting times is large is given priority and data from FIFO 51 having mush data is given priority in the request mask circuit 61 by a counter over signal from the comparator 57 comparing the waiting number counter 55 counting the number of waiting times for data with the value of the threshold register 56 in respective cross bus switches. Thus, the throughput of respective input/output ports is changed by giving priority to data in the input buffer having mush data amount, and the use efficiency of the buffer can be improved.

8. 发明专利

JPH02132545A PARALLEL COMPUTER AND ITS COMPILING METHOD 失效
公开(公告)号：JPH02132545A
公开(公告)日：1990-05-22
申请号：JP28565088
申请日：1988-11-14
申请人： HITACHI LTD
发明人： TANAKA TERUO , NAGASHIMA SHIGEO , OMODA KOICHIRO , NAKAKOSHI JUNJI , HAMANAKA NAOKI , OSHIMA KAZUO
IPC分类号： G06F11/28 , G06F9/45 , G06F15/16 , G06F15/177
摘要： PURPOSE:To detect the bug of a program that occurs when the data are transferred between processors or the data are processed synchronously with each other by changing the performance of the element processor for each element program. CONSTITUTION:When the performance (instruction executing speed) of a certain element processor PE is changed, the number of the relevant processor is sent to the PE 3-1 to 3-3 from a host processor 1 via a line l20. Each PE compares its own number held in a register 8 of an instruction decoding part with the PE number received from the processor 1 via a comparator 9. When the coincidence is obtained between both numbers, an NOP (no operation) inserting circuit 10 is started. The circuit 10 switches a selector 14 in order to send the NOP instructions to a decoder 13 every second instruction. Thus it is possible to change the performance of a certain PE and to dynamically change the states among PEs to serve as an aid to detect the bug in the transfer of data or the sequence control among the PEs.

9. 发明专利

JPS6354668A PIPELINE COMPUTING ELEMENT 失效
公开(公告)号：JPS6354668A
公开(公告)日：1988-03-09
申请号：JP19711986
申请日：1986-08-25
申请人： HITACHI LTD
发明人： NAKAKOSHI JUNJI , OMODA KOICHIRO , INAGAMI YASUHIRO , HAMANAKA NAOKI
IPC分类号： G06F17/16 , G06F15/78
摘要： PURPOSE:To speed up the operation of a scalar processing and a vector processing by providing a clock control circuit which controls the clock of a register holding the operated results in the respective operational stages of a pipeline computing element. CONSTITUTION:In case of executing the following vector processing or the scalar processing, at the time when it is assured the operated results of the scalar process can pass without stopping through the register of the respective operational stages, that means, after the clock 120 of the register holding inputted data which should be operated in the scalar process is generated, the clocks 121-124 are sequentially generated after one cycle in order not to pass without stopping through the registers R2-R5 of the respective operational stages 130-134. And after the clock 120 which holds inputted data which should be operated in the scalar process is generated, the clocks 120-125 of the registers R1-R6 are sequentially generated after two cycles in order to obtain the operated results according to the respective operational stages. Thus, the operated results can be obtained in the least waiting time.

10. 发明专利

JP2000194676A PARALLEL COMPUTER WITH DATA TRANSFER MECHANISM 失效
公开(公告)号：JP2000194676A
公开(公告)日：2000-07-14
申请号：JP37277198
申请日：1998-12-28
申请人： HITACHI LTD
发明人： FUJII KEIMEI , YASUDA YOSHIKO , SAGAWA NOBUTOSHI , SUZUKI ATSUHIRO , NAKAKOSHI JUNJI
IPC分类号： G06F15/173 , G06F9/46 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To eliminate the overhead of a software process and a process flow by obtaining write destination address information on received data by referring to the contents of an information storage means when the data are received and writing the received data in a memory in sequence. SOLUTION: A message header analysis part 106 which becomes receivable starts writing transfer data in a transfer message to a local main storage. When this process starts, the transfer data (received data) are passed from the message header analysis part 106 to a received data writing process part 122. The received data writing process part 122 sequentially generates requests for write access to the local main storage for the received data by using the received data and write destination address information on the received data sent from a receiving buffer management part 109 and sends them to a storage controller 502 through a storage controller interface 101, and the storage controller 502 sends write requests to the local main storage.

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