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1. 发明专利

JPH06282511A FAULT PROCESSING DEVICE OF COMPUTER SYSTEM HAVING NETWORK 失效
公开(公告)号：JPH06282511A
公开(公告)日：1994-10-07
申请号：JP33053193
申请日：1993-12-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKEUCHI SHIGEO , INAGAMI YASUHIRO , NAKAKOSHI JUNJI , SHUDO SHINICHI , HIGUCHI TATSUO , FUJII KEIMEI , YASUDA YOSHIKO , OBARA KIYOHIRO , TOBA TATSU , YAMADA MASAHIRO
IPC分类号： G06F11/00 , G06F13/00 , G06F15/16 , G06F15/177
摘要： PURPOSE:To provide a network which does not affect on other message transfer even if any fault occurs in the process of a message transfer. CONSTITUTION:The fault detected by a fault detector 102 is held in a fault holding register A 110 or a fault holding register B 111, and the detected word number is held in a fault word number holding register 112. When a message generation circuit 120 judges that they are inputted and the fault is detected by a transfer destination processor number, the circuit 120 outputs a message to the processor shown by the transfer destination processor number at the time of the occurrence of the fault to be delivered from a selector 109. Because the message is made to be transferred to a proper processor in place of the transfer destination processor when a fault occurs in the transfer destination processor number of the message, the message does not stop in the network and does not affect on other message transfer.

2. 发明专利

JPH06266682A NETWORK FOR PARALLEL COMPUTER 失效
公开(公告)号：JPH06266682A
公开(公告)日：1994-09-22
申请号：JP8013193
申请日：1993-03-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YASUDA YOSHIKO , NAKAKOSHI JUNJI , SHUDO SHINICHI , FUJII KEIMEI , HIGUCHI TATSUO , TAKEUCHI SHIGEO
IPC分类号： G06F15/173 , G06F15/16
摘要： PURPOSE:To provide plural connections without reducing transfer width between processors, and to realize interlaced transfer jumping over several processors. CONSTITUTION:Network switching circuits (SE) 109 to 116 are installed between adjacent interconnection switches (EX) 105 to 108. SE is connected to the adjacent interconnection switch by a data line, and simultaneously, it is connected to SE distant by plural stages by the data line, and when a network switching signal from a host computer instructs adjacent transfer, it transfers data inputted from the data line to adjacent EX, and at the time of the instruction of the interlaced transfer, it transfers the data to SE distant by plural stages. When the network switching signal instructs the adjacent transfer, it separates the data, and sends it to the data line to adjacent EX and the data line to SE, and at the time of the instruction of the interlaced transfer it sends all the data to the data line to ES.

3. 发明专利

JPH06250981A PROCESSOR ELEMENT HAVING CACHE MEMORY WITH RESERVE FUNCTION AND COMPUTER SYSTEM CONSISTING OF THE SAME 失效
公开(公告)号：JPH06250981A
公开(公告)日：1994-09-09
申请号：JP3172993
申请日：1993-02-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TOBA TATSU , INAGAMI YASUHIRO , NAKAKOSHI JUNJI , SHUDO SHINICHI , HIGUCHI TATSUO , FUJII KEIMEI , YASUDA YOSHIKO , OBARA KIYOHIRO , TAKEUCHI SHIGEO , YAMADA MASAHIRO
IPC分类号： G06F12/08 , G06F13/12 , G06F15/16
摘要： PURPOSE:To reduce overheads when data are transmitted to and accepted from plural processors with cache memories. CONSTITUTION:A reserve bit R which allows a reception unit 12 to set and reset each entry is provided on an address array 104 managing each entry of a cache memory 21 of a processor 10. The entry with the reserve bit is removed from the object of a block replace. In prior to the reception, the reserve bit is set to the entry where the reception data are written. At the time of reception, the reception data are written in the entry where the reserve bit is set. Thus, the possibility of the cache memory making erroneous hits is reduced and the overhead can be reduced.

4. 发明专利

JP2014216991A 分析サーバ及び分析方法有权
标题翻译：分析服务器和分析方法
公开(公告)号：JP2014216991A
公开(公告)日：2014-11-17
申请号：JP2013095226
申请日：2013-04-30
申请人：株式会社日立製作所 , Hitachi Ltd
发明人： YAMADA MARIKO , UMEMURA MASAYA , YASUDA YOSHIKO
IPC分类号： H04L12/70 , G06F13/00
CPC分类号： G06F13/00
摘要：【課題】実運用時にテナントシステムの通信パケットが経由するネットワークの状態を分析する際、分析に要する時間を削減する。【解決手段】計算機が、テナントの情報処理システムのネットワークを構成するノードの構成情報に基づいて、通信記録情報を収集するノードを選択し、選択したノードに通信記録情報を収集させ、収集された通信記録情報を取得して、ネットワークの状態を分析し、ネットワークにおいて分析対象レイヤの端点となるノード間で通信パケットの通信経路を計算し、分析対象レイヤの第1の端点となる第1のノードの通信記録情報と、第2の端点となる第2のノードの通信記録情報とを比較して、第1のノードの通信パケットが第2のノードに到達したことを判定し、第2のノードに未到達の通信パケットを廃棄したノードを特定する。【選択図】図5
摘要翻译：要解决的问题：在实际操作期间分析在其中发送租户系统的通信分组的网络的状态分析时，减少分析所需的时间。解决方案：计算机基于以下方式选择节点来收集通信记录信息：形成租户信息处理系统网络的节点的配置信息使所选择的节点收集通信记录信息，并且通过获取所收集的通信记录信息来分析网络的状态。在作为网络中的分析对象层的终点的节点之间计算通信分组的通信路由，将作为分析对象层的第一终点的第一节点的通信记录信息与通信记录信息的通信记录信息进行比较第二节点作为第二终端点，确定第一节点的通信分组到达第二节点，并且识别尚未到达第二节点的通信分组的节点。

5. 发明专利

JP2003345643A Method and apparatus for virtual unification of network storage system 有权
标题翻译：网络存储系统虚拟统一的方法与装置
公开(公告)号：JP2003345643A
公开(公告)日：2003-12-05
申请号：JP2002149977
申请日：2002-05-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAWAMOTO SHINICHI , EBATA ATSUSHI , OKITSU JUN , YASUDA YOSHIKO , HIGUCHI TATSUO
IPC分类号： G06F3/06 , G06F12/00 , G06F13/00 , G06F15/16
CPC分类号： G06F3/0611 , G06F3/0631 , G06F3/0643 , G06F3/067 , Y10S707/99952 , Y10S707/99953
摘要： PROBLEM TO BE SOLVED: To compactly hold information not in proportion to the number of the files on a network storage to which a file is stored in a virtual unifying method for a network storage system in which one or more network storages are virtually unified.
SOLUTION: The files are divided into one or more file groups and the storage destination storages are managed group by group.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：在一个或多个网络存储器虚拟的网络存储系统的虚拟统一方法中，紧凑地保存与文件所存储的网络存储器上的文件数量不成比例的信息统一。解决方案：将文件分为一个或多个文件组，并逐组管理存储目标存储。版权所有（C）2004，JPO

6. 发明专利

JP2002182948A TRACE ACQUISITION METHOD AND DEVICE 失效
公开(公告)号：JP2002182948A
公开(公告)日：2002-06-28
申请号：JP2000379769
申请日：2000-12-08
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： YASUDA YOSHIKO , HIGUCHI TATSUO , HAMANAKA NAOKI , SHUDO TAKASHI , TSUJII HIDEAKI
IPC分类号： G06F11/28
摘要： PROBLEM TO BE SOLVED: To provide a trace device and a trace acquisition method for efficiently utilizing a memory and reducing the labor of debugging and tuning a user program. SOLUTION: The trace device is provided with a trace management table holding one or more trace write end addresses and a means for generating a trace write address. At the time of starting trace acquisition, the trace write address generation means reads the write end address held in the trace management table and generates a new trace write address. A means for registering the trace write address to the trace management table when the trace acquisition is ended is provided.

7. 发明专利

JPH11345220A INTER-NODE DATA TRANSFER METHOD AND INTER-COMPUTER DATA TRANSFER METHOD 失效
公开(公告)号：JPH11345220A
公开(公告)日：1999-12-14
申请号：JP16928398
申请日：1998-06-02
申请人： HITACHI LTD
发明人： NAONO TAKESHI , YAMAMOTO YUSAKU , IHARA SHIGEO , ITO SATOSHI , YASUDA YOSHIKO
IPC分类号： G06F15/173 , G06F13/38 , G06F15/163
摘要： PROBLEM TO BE SOLVED: To execute data transfer which makes the whole data to be transferred exist on the whole memories in the shortest time. SOLUTION: This data transfer method performs one side transfer and mutual transfer with other computers and is performed by a parallel computer that consists of plural computers provided with a memory and performs the fastest data transfer by performing mutual transfer two times after performing one side transfer two times at the time of transferring data so as to be stored in the whole computers, for instance, when data D(1) is stored is M(12) among computers 1 to 16 (memories M(1) to M(16)), D(2) in M(10), D(3) in M(11) and D(4) in M(12). Generally, when there are M computers (however, M is the power of 2) and D pieces (however, 1

8. 发明专利

JPH10214259A PARALLEL COMPUTER 失效
公开(公告)号：JPH10214259A
公开(公告)日：1998-08-11
申请号：JP2972297
申请日：1997-01-29
申请人： HITACHI LTD
发明人： FUJII KEIMEI , YASUDA YOSHIKO
IPC分类号： G06F9/46 , G06F15/16 , G06F15/163 , G06F15/17
摘要： PROBLEM TO BE SOLVED: To realize the sharing mechanism of a main storage content at low costs, and to attain the efficient improvement of a coordinated processing between element processors in a parallel computer in a distributed memory system. SOLUTION: A mirror group sharing a main storage content between element processors is defined, and a mirror page corresponding to the group (id) is prepared on a main storage 118 of each element processor. Also, a storage controller 102 is provided with a mirror table 105 which registers the leading address of the mirror page and the group (id), and a main storage writing request in the mirror page is detected by an address analyzing part 104 by referring to the table 105, and the writing request is transmitted to the main storage 118, and also transmitted through an interconnection network 202 to the whole element processors in the mirror group. Thus, a page having the same main storage content is allowed to exist in each element processor in the mirror group, and the pseudo-sharing of the main storage content can be attained.

9. 发明专利

JPH09198358A PROBLEM AREA DIVISION/ALLOCATION SYSTEM AND COMPUTER LIBRARY USING THE SAME 失效
公开(公告)号：JPH09198358A
公开(公告)日：1997-07-31
申请号：JP895796
申请日：1996-01-23
申请人： HITACHI LTD
发明人： YASUDA YOSHIKO , TANAKA TERUO
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , G06F15/80
摘要： PROBLEM TO BE SOLVED: To provide communication performance equal to that at the time of allocating an area with being conscious of dimensional constitution even if the problem area is divided and the divided area is allocated to a processor without being conscious of the dimensional constitution of a parallel computer by means of a user. SOLUTION: In the parallel computer which has a network containing grid torus connection in which the number N of the processors can be displayed by the n-th power of a prime (x) (>=2), a means 1-1 for deciding the number (m) of dimensions on the problem area in a range which does not exceed (n), a means 1-3 for deciding an area division method among area division methods satisfying the power of logx N>=logx (n1 ×n2 ×n3 ×...×n), n1 , n2 , n3 ,..., and n=x(>=2) when the number of the respective dimensional grids of a physical space is set to be n1 , n2 , n3 ,..., and a means 1-4 for allocating the devided area to the processor having the same physical number as a divided area number which is one-dimensionally displayed are provided.

10. 发明专利

JP2012182605A Network control system and administrative server 审中-公开
标题翻译：网络控制系统和管理服务器
公开(公告)号：JP2012182605A
公开(公告)日：2012-09-20
申请号：JP2011043499
申请日：2011-03-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAYAMA MARIKO , YASUDA YOSHIKO , OKITA HIDEKI
IPC分类号： H04L12/56
摘要： PROBLEM TO BE SOLVED: To minimize data transfer time in a system configured in a data center while avoiding unnecessary communication for observing surplus bands and improving utilization rates of physical bands.SOLUTION: A network control system manages communication flows of servers configuring an information processing system of a tenant and physical communication paths through which respective communication flows pass. Further, the network control system monitors band utilization rates of respective interfaces and band utilization rates of respective communication flows in the physical communication paths and changes control methods applying to the communication flows according to respective utilization rates so as to minimize data transfer time.
摘要翻译：要解决的问题：为了最小化配置在数据中心的系统中的数据传输时间，同时避免不必要的通信以观察剩余频带并提高物理频带的利用率。解决方案：网络控制系统管理配置租户的信息处理系统的服务器的通信流和通过各个通信流的物理通信路径。此外，网络控制系统监视物理通信路径中的各个通信流的各个接口的频带利用率和频带利用率，并且根据各自的利用率改变应用于通信流的控制方法，从而最小化数据传送时间。版权所有（C）2012，JPO＆INPIT

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