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1. 发明专利

JP2000196571A PHASE ADJUSTMENT SYSTEM 失效
公开(公告)号：JP2000196571A
公开(公告)日：2000-07-14
申请号：JP36676998
申请日：1998-12-24
申请人： HITACHI LTD
发明人： SUZUKI ATSUHIRO , NAKAJIMA KAZUNORI , OGIWARA MASAO
IPC分类号： H04L7/00 , H04L7/02
摘要： PROBLEM TO BE SOLVED: To set a phase of a plurality of different transmission paths in a short time and to set a phase where an operating margin is maximized even when a spread of a data uncertain area is smaller than a delay unit of a variable delay circuit. SOLUTION: A transmission section 1 is provided with a phase adjustment pattern generating means 13 that generates phase adjustment pattern data that increases a noise quantity. A reception section 2 corresponding to the transmission section 1 is provided with a variable delay means 21 that optionally delays transmission data, a data check means 23 that checks whether or not the phase adjustment pattern data outputted from a reception latch 22 is correct, an edge detection means 24 that detects an uncertain area of the phase adjustment pattern data just before the reception latch 22, and a phase control means 25 that sequentially changes a delay of the variable delay means 21 and sets an optimum delay by using the check detection result of the means 23, 24 according to the change.

2. 发明专利

JP2002341974A HARDWARE RESET SYSTEM BY PROGRAM 失效
公开(公告)号：JP2002341974A
公开(公告)日：2002-11-29
申请号：JP2001150268
申请日：2001-05-21
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： IKETANI KATSUNORI , ISHITANI KAZUHIRO , UEDA AKIHIRO , MIYAMOTO AKIRA , SUZUKI ATSUHIRO
IPC分类号： G06F9/38 , G06F1/24
摘要： PROBLEM TO BE SOLVED: To efficiently achieve initialization of hardware corresponding to every piece of hardware even to update of the hardware in a device and change of hardware configuration by initialization data. SOLUTION: This hardware reset system is provided with a temporary storage to hold a reset program and the initialization data, a control circuit to store the reset program and the initialization data in the temporary storage via a communication line and to initialize the hardware by controlling start and stop of the program stored in the temporary storage by a start stop control bus to transfer information about the hardware to be an object of initialization, information about the initialization data, start and termination and a setting path to connect the control circuit to read a state and management information of the hardware and to set the initialization data with the respective pieces of hardware.

3. 发明专利

JPH05181817A PARALLEL PROCESSOR 失效
公开(公告)号：JPH05181817A
公开(公告)日：1993-07-23
申请号：JP9861591
申请日：1991-04-30
申请人： HITACHI LTD , YOSHIOKA YOSHIO
发明人： SUZUKI ATSUHIRO , YOSHIOKA YOSHIO
IPC分类号： G06F13/36 , G06F15/16 , G06F15/163 , G06F15/173 , G06F15/80 , G06F15/82
摘要： PURPOSE:To constitute a parallel processor so that the burden of a packet controller is reduced, the packet controller can allow more data packets to flow to a high speed packet processor and many tasks can be subjected efficiently to multiple processing in parallel by forming a structure in which plural PEs are connected to a pipeline type ring bus as one layer and connecting successively respective layers. CONSTITUTION:The pipeline type ring bus of one layer in which plural shift registers are connected like a ring is provided with plural layers (10, 20, 30), and also, processing means for fetching and processing a packet flowing on the pipeline type ring bus are provided on respective shift registers of respective layers (211-214, 221-224, 231-234), and moreover on at least one processing means of each layer, a packet control means 102 for transferring the packet is provided, and to the processing means, a means for fetching the output of the processing of the upper layer of the layer for which the means belongs to the pipeline type ring bus of its own layer is imparted.

4. 发明专利

JP2002111774A PROCESSOR AND PARALLEL PROCESSING SYSTEM 失效
公开(公告)号：JP2002111774A
公开(公告)日：2002-04-12
申请号：JP2000301585
申请日：2000-10-02
申请人： HITACHI LTD
发明人： NAKAKOSHI JUNJI , SUZUKI ATSUHIRO , KAWAMURA TOSHIO
IPC分类号： G06F15/177 , G06F12/00 , H04L12/28 , H04L12/70 , H04L29/02 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To make it possible to generate a transmission demand during of transmission in a processor of transmission and receiving operation of a packet. SOLUTION: A transmission start register 131 for setting an address of a transfer control word block(TCWB) 160 as a transmission demand, a transmission state register 134 for indicating the state during transmission process in a transmission circuit, and a queue register 132 for joining a new TCWB to the TCWB during the transmission process are provided. When a new transmission demand is generated during indication of transmission process of the transmission state register 134, a command processor 107 sets a TCWB address for the new transmission demand in the queue register 132. A transmission circuit 103 refers to the queue register 132 after the transmission process is completed on the basis of the TCWB. When the TCWB address is set, the TCWB address is set to the transmission start register 131 and the transmission process is carried out continuously.

5. 发明专利

JP2001202345A PARALLEL PROCESSOR 失效
公开(公告)号：JP2001202345A
公开(公告)日：2001-07-27
申请号：JP2000017738
申请日：2000-01-21
申请人： HITACHI LTD
发明人： NAKAKOSHI JUNJI , SUZUKI ATSUHIRO
IPC分类号： G06F15/177 , G06F15/163 , G06F15/17 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To solve a problem it can not be confirmed whether each of divided packets is normally received or not for each packet when transferring transfer data on a network while dividing them into plural packets. SOLUTION: Transmitting data are divided into arbitrary packet size without overhead of software and generated into packet for the unit of a divided transmitting data length. Information capable of confirming whether the packet is normally received or not each time receiving this packet is transmitted while being applied to the header of each of packets.

6. 发明专利

JP2000194676A PARALLEL COMPUTER WITH DATA TRANSFER MECHANISM 失效
公开(公告)号：JP2000194676A
公开(公告)日：2000-07-14
申请号：JP37277198
申请日：1998-12-28
申请人： HITACHI LTD
发明人： FUJII KEIMEI , YASUDA YOSHIKO , SAGAWA NOBUTOSHI , SUZUKI ATSUHIRO , NAKAKOSHI JUNJI
IPC分类号： G06F15/173 , G06F9/46 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To eliminate the overhead of a software process and a process flow by obtaining write destination address information on received data by referring to the contents of an information storage means when the data are received and writing the received data in a memory in sequence. SOLUTION: A message header analysis part 106 which becomes receivable starts writing transfer data in a transfer message to a local main storage. When this process starts, the transfer data (received data) are passed from the message header analysis part 106 to a received data writing process part 122. The received data writing process part 122 sequentially generates requests for write access to the local main storage for the received data by using the received data and write destination address information on the received data sent from a receiving buffer management part 109 and sends them to a storage controller 502 through a storage controller interface 101, and the storage controller 502 sends write requests to the local main storage.

7. 发明专利

JPH086908A BRANCH PROCESSING SYSTEM FOR PARALLEL PROCESSOR 失效
公开(公告)号：JPH086908A
公开(公告)日：1996-01-12
申请号：JP14188194
申请日：1994-06-23
申请人： HITACHI LTD
发明人： SUZUKI ATSUHIRO
IPC分类号： G06F9/38 , G06F15/16 , G06F15/80
摘要： PURPOSE:To efficiently operate an instruction pipeline for processors by preventing the instruction pipeline from being disturbed by a branch instruction and. eliminating an unnecessary access to a main storage and interruption processing requiring long period. CONSTITUTION:A main processor 1 generates sub-programs for a program to be processed so that a branch condition for a branch instruction is always invalid and allocates these sub-programs to respective sub-processors 2a to 2d to execute them. Each of the sub-processors 2a to 2d executes abnormal end when the branch instruction is valid in the processing of the sub-program, and at the time of ending the processing without validating the branch instruction, reports normal end to the main processor 1. The processor 1 adopts the processing result of the sub-processor ending its processing without validating the branch instruction as the processing result of the program to be processed.

8. 发明专利

JPH04195362A PROCESSING SYSTEM FOR ADDITION INSTRUCTION WITH MEMORY EXCLUSIVE CONTROL 失效
公开(公告)号：JPH04195362A
公开(公告)日：1992-07-15
申请号：JP32255390
申请日：1990-11-28
申请人： HITACHI LTD
发明人： SUZUKI ATSUHIRO , NAKAGAWA YAOKO
IPC分类号： G06F15/16 , G06F9/52 , G06F15/177
摘要： PURPOSE:To shorten the processing time by adding an addition value to data in a common variable area placed in an exclusive state by and writing the addition result back to the common variable area by processors with the addition instruction with memory exclusive control of the system consisting of the processors and a storage controller. CONSTITUTION:While the common variable area of a storage device 3 is brought under exclusive control so as to speed up the addition processing, the addition processing which uses a fetch-and-add instruction. When the addition instruction with memory exclusive control is executed, the storage device 3 is controlled exclusively and it is decided whether or not the addition value specified by the instruction word can be added by an adder 21 in the storage controller 2. According to the decision result, the addition value read out of the common variable area of the storage device 3 and data supplied from the processor 1a are added by the adder 21 in the storage controller 2 or a computing element 12a in the processor 1a and the addition result is written in the storage device 3.

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