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1. 发明专利

JP2003133437A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：JP2003133437A
公开(公告)日：2003-05-09
申请号：JP2001326757
申请日：2001-10-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KUJIRAI YUTAKA , SHIGENIWA MASAHIRO , NAKAZATO KAZUO , KISU TERUAKI , MATSUOKA HIDEYUKI , TABATA TAKESHI , HAGA SATORU
IPC分类号： H01L21/768 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device having a vertical transistor for memory cell selection. SOLUTION: A vertical MIS Qvn is provided immediately on a grooved capacitor 6 provided to a semiconductor substrate 1S in a memory cell region, and a lateral nMIS Qn is provided to a semiconductor substrate in a peripheral circuit region. After the capacitor 6 is formed, a lateral nMIS Qn is formed. After a lateral nMIS Qn is formed, a vertical MIS Qvn is formed. Furthermore, after a capacitor is formed, a separation part 10 of a peripheral circuit region is formed.

2. 发明专利

JPH0864525A FORMING METHOD OF CRYSTALLINE PARTICLES AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0864525A
公开(公告)日：1996-03-08
申请号：JP19815394
申请日：1994-08-23
申请人： HITACHI LTD
发明人： SHIGENIWA MASAHIRO , NISHIDA AKIO , MURAKAMI HIDEKAZU , KUJIRAI YUTAKA
IPC分类号： H01L21/20 , H01L21/205 , H01L29/66 , H01L33/04 , H01L33/00
摘要： PURPOSE: To provide a process of forming extremely fine size crystalline particles in diameter of 10-40Å to produce unit electronic elements and shortwave Si light-emitting elements having high reliability. CONSTITUTION: Fine particles in extremely fine size are deposited while maintaining the low temperature not exceeding the lower limit substrate temperature for crystalline phase deposition. These amorphous fine particles are made into extremely fine size by heat-treating at the temperature exceeding crystallizing temperature. A semiconductor device is structured of the crystalline fine particles held between insulating thin films and further between conductive materials. Next, the conductive materials are impressed with a voltage so as to implant the crystalline fine particles with a tunnel current for emitting light. Such unit elements can form a large-capacity, high-speed low-power LSI and blue-green light-emitting devices, which realize an optoelectronic system for transferring and processing a large amount of data.

3. 发明专利

JPH08133881A METHOD FOR FORMING CRYSTALLINE THIN MEMBRANE 失效
公开(公告)号：JPH08133881A
公开(公告)日：1996-05-28
申请号：JP27332494
申请日：1994-11-08
申请人： HITACHI LTD
发明人： SHIGENIWA MASAHIRO , MURAKAMI HIDEKAZU , KUJIRAI YUTAKA , KIYOTA YUKIHIRO
IPC分类号： C30B1/02 , H01L21/20 , H01L21/203
摘要： PURPOSE: To provide a method for forming a good crystalline thin membrane in the process of piling the thin membrane consisting of a second material on a base plate consisting of a first material, then heat-treating the membrane for crystallization, first by piling the second material upto the thickness of the lattice constant from the first atomic layer while keeping the migration distance of the constituting atoms of the second material to its lattice constant or less, then piling the material upto the required thickness by making the migration distance larger than the lattice distance. CONSTITUTION: This method for forming a crystalline thin membrane comprises using e.g. SiO2 as a first material and Si as a second material. By conducting the piling of a membrane with a long migration distance, the density of the membrane becomes non uniform and the crystallinity of the solid phase grown membrane becomes low. Therefore, in this method, once the material is piled thinly with the short migration distance and then piled upto the required thickness with the long migration distance. Once spreading Si atoms over uniformly by piling at a low temperature, countless unbonded Si-linkages are protruding uniformly on the surface of the base plate.

4. 发明专利

JPH06216376A FIELD EFFECT TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06216376A
公开(公告)日：1994-08-05
申请号：JP564393
申请日：1993-01-18
申请人： HITACHI LTD
发明人： KUJIRAI YUTAKA , MURAKAMI HIDEKAZU
IPC分类号： H01L21/316 , H01L21/335 , H01L29/36 , H01L29/78 , H01L29/784
摘要： PURPOSE:To provide a semiconductor device having a gate insulating film without deforming SiGe/Si heterostructure and the profile of doping of impurities, by depositing an oxide film which makes a semiconductor substrate one or the components, and an insulating film, on the semiconductor substrate having an impurity layer wherein the impurity distribution is specified. CONSTITUTION:On Si and SiGe/Sl heterostructure wherein the spread of impurity distribution is smaller than 10nm, a thermal oxide film of 5nm or smaller in thickness is formed at 800 deg.C, and thereon an insulating film is deposited. For example, Si layers 12, 14 having a delta doping layer of B are epitaxially grown on a silicon substrate 11, and the surface is oxidized to be 2nm thick at 800 deg.C, thereby forming an oxide film 15. An insulating film 16 of 3nm in thickness is deposited on the film 15 by a plasma CVD method. A gate insulating film having necessary thickness can be formed without deteriorating the SiGe heterointerface and the sharpness of a doping profile.

5. 发明专利

JP2002100746A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002100746A
公开(公告)日：2002-04-05
申请号：JP2000286381
申请日：2000-09-21
申请人： HITACHI LTD
发明人： KUJIRAI YUTAKA , SHIGENIWA MASAHIRO
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a technique by which the retention time of the memory cell of a DRAM can be improved by suppressing the punch through phenomenon of a MISFET constituting the memory cell, etc., of the DRAM. SOLUTION: A threshold adjusting impurity region SA3 is formed in a semiconductor substrate under the p-type gate electrode 9p of the MISFET Qs for information transfer of the DRAM through implanting, for example, of BF ions into the region. In addition, a punch through preventive region PA is formed in the semiconductor substrate at a position deeper than the region SA3, so as to cover the end sections of the source and drain of the MISFET Qs by implanting ions of an impurity, for example, In which are atoms heavier than those of the threshold adjusting impurity has into the region.

6. 发明专利

JP2000021878A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000021878A
公开(公告)日：2000-01-21
申请号：JP18996198
申请日：1998-07-06
申请人： HITACHI LTD
发明人： OKADA MANABU , KUJIRAI YUTAKA
IPC分类号： H01L21/3205 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To reduce the generation of cracks of a passivation film due to a filler in a sealing material. SOLUTION: The inter-wiring distance of a third layer wiring M3 which is the uppermost layer wiring is set as a distance d1, sufficiently smaller than the grain diameter (2.X) of a filler 20, for example, 1 μm or smaller, or a distance d2 sufficiently larger than the grain diameter of the filler 20, for example, 4 μm or larger. Also, the distance d2 can be set as 2(x+y) cosθ or larger. In this case, (x) is a radius x of the filler 20, and (y) is a distance y from the upper edge of the third layer wiring M3 until the contact point of a passivation film 17 with the filter 20, and θ is an angle θ made by a face, including the central point of the filter 20, in parallel with a semiconductor substrate 1 and a radius vector drawn from the central point to the contact point.

7. 发明专利

JPH08241984A FABRICATION OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08241984A
公开(公告)日：1996-09-17
申请号：JP4382495
申请日：1995-03-03
申请人： HITACHI LTD
发明人： MURAKAMI HIDEKAZU , KUJIRAI YUTAKA , TAKEMURA YOSHIAKI , KIMURA SHINICHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L27/092
摘要： PURPOSE: To sufficiently recover the crystallinity of a deeply diffused layer by previously forming a deeply diffused layer using a side wall spacer made of a polycrystal line silicon to control impurity diffusion of a shallow diffused layer while controlling a junction leak current. CONSTITUTION: After formation of P-type well 11, N-type well 12, oxide film 13 for element isolation and gate oxide film 14 on an Si substrate 10, a gate electrode 15 made of polycrystal line Si is formed. After the formation of the gate, a CVD SiO2 film 120 is deposited, a polycrystal line Si film 16 is then deposited, and it is processed into a polycrystal line Si side wall spacer 17 by the anisotropic etching process. Next, the As ions 19 are implanted into the N-MOS FET forming region using the photoresist 18 as a mask and BF3 ions 111 are implanted into the P-MOS FET forming region. After the etching and heat treatment, a deep N-type diffused layer 110 and a deep P-type diffused layer 112 are formed. Moreover, with further processing, a titanium silicide layer is finally formed at the upper part of the deeply diffused layer and gate electrode.

8. 发明专利

JP2000236074A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000236074A
公开(公告)日：2000-08-29
申请号：JP30911499
申请日：1999-10-29
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , OGISHIMA JUNJI , TSUCHIYA OSAMU , TADAKI YOSHITAKA , WATABE KOZO , UCHIYAMA HIROYUKI , IKEDA YOSHIHIRO , OKAZAKI TSUTOMU , ASAKURA HISAO , KAWAKITA KEIZO , SHIGENIWA MASAHIRO , KUBOTA KATSUHIKO , KUJIRAI YUTAKA , KAJITANI KAZUHIKO , NAGASHIMA YASUSHI , NAKAMURA MASAYUKI
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable DRAM by obtaining a desired threshold voltage in a memory cell and at the same time improving refresh characteristics. SOLUTION: A threshold voltage of 1.1 V of a memory cell selecting MISFET (Qs) is obtained by forming a p-type semiconductor region 27 and n--type semiconductor regions 8a, 8b whose impurity concentration is relatively high in a p-type well 4 on a data line side of the memory cell selecting MISFET (Qs). Junction field strength near the end part at an information storing capacity element side of a gate electrode 7a is reduced, by not forming the p-type semiconductor region 27 in the p-type well 4 at an information storing capacity element side but by forming the n--type semiconductor region 8b whose impurity concentration is relatively low.

9. 发明专利

JPH097962A FORMATION METHOD OF BORON-DOPED LAYER AND SEMICONDUCTOR DEVICE USING IT 失效
公开(公告)号：JPH097962A
公开(公告)日：1997-01-10
申请号：JP14854695
申请日：1995-06-15
申请人： HITACHI LTD
发明人： USHIO JIRO , TAKEMURA YOSHIAKI , MARUIZUMI TAKUYA , IRIE RYOTARO , YAMAGUCHI KEN , MURAKAMI HIDEKAZU , KIMURA SHINICHIRO , KUJIRAI YUTAKA
IPC分类号： H01L21/22 , H01L21/205
摘要： PURPOSE: To reduce the troubles of thermal diffusion of boron and a bad influence of boron on another layer structure on a silicon substrate by employing a boron hydride molecule including four or more boron atoms as a boron source. CONSTITUTION: Several layers of Sb atoms 29 are selectively adsorbed onto a Si surface. Then, substrate temperature is raised to 600 to 700 deg.C to leave only Sb atoms 29 corresponding to one atom layer bonded to the Si surface. At this time also a hydrogen mask composed of remaining hydrogen atoms 26 is eliminated. Then, B4 H10 molecules 210 are introduced and adsorbed onto the surface. The adsorption of the B4 H10 molecules 210 are produced at substrate temperature of 300 deg.C selectively only in a region where no Sb atom 29 is existent. More specifically, a B4 H10 molecule layer pattern is formed in a self alignment manner for an Sb atom layer pattern. Hereby, there can be reduced thermal diffusion of boron and a bad influence of boron on other layer structures on a silicon substrate.

10. 发明专利

JPH07115137A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07115137A
公开(公告)日：1995-05-02
申请号：JP26210393
申请日：1993-10-20
申请人： HITACHI LTD
发明人： KUJIRAI YUTAKA , MURAKAMI HIDEKAZU , KIMURA SHINICHIRO
IPC分类号： H01L27/092 , H01L21/8238
摘要： PURPOSE:To enable a semiconductor device to be lessened in number of manufacturing processes and protected against contamination caused by heavy metals by a method wherein an Si substrate is locally irradiated with excimer laser ray to form an Si oxide film, and the Si oxide film is selectively grown and then removed in a vacuum by heating. CONSTITUTION:The surface of an Si substrate 11 isolated by an oxide film 12 is locally irradiated with excimer laser ray 13 in an oxidizing atmosphere for the formation of an Si oxide film 14. Then, an Si film 15 is epitaxially grown with gas such as SiH4, Si2H6, or SiH2Cl2 on a part of the substrate 11 where no oxide film is present. Thereafter, the Si substrate 11 is heated in a vacuum to remove the Si oxide film 14 by sublimating. By this setup, as only processes of oxidation, epitaxial growth., and sublimation of oxide film are used, a semiconductor crevice of this constitution can be lessened in number of manufacturing processes and protected against contamination caused by heavy metals which are usually mixed into the device accompanying the use of organic photoresist or the implantation of ions.

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