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1. 发明专利

JPH11164317A VIDEO SIGNAL PROCESSING UNIT 失效
公开(公告)号：JPH11164317A
公开(公告)日：1999-06-18
申请号：JP32643897
申请日：1997-11-27
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MAYUZUMI SHIRO , YAMAZAKI KOICHI , HIRANO TOSHIAKI , KAMEGAKI KAZUYUKI , HOSHINO KATSUMI , NAKAGAWA TADASHI , ICHIKAWA YOSHIHISA , OKADA YOSHITAKA , MORI SHUNJI , TAKAYAMA ETSUTAKA , KITAMURA YUKINORI , KOBAYASHI YUJI , TAKEBUCHI KENJI , KURIHARA TAKASHI
IPC分类号： H04N9/793
摘要： PROBLEM TO BE SOLVED: To provide the technology that suppresses a crosstalk up to a practical level and attains one chip processing of a recording and reproducing preamplifier and a luminance signal and color signal processing circuit. SOLUTION: A recording and reproducing preamplifier 2 and a luminance signal and color signal processing circuit 3 are formed on one semiconductor chip. Then a mode changeover control circuit (logic circuit section having a changeover control circuit 4) consisting of an IIL (integrated injection logic) having been included in the circuits 2, 3 is placed between the recording and reproducing preamplifier 2 and the luminance signal and color signal processing circuit 3 to surround the IIL circuit around the recording and reproducing preamplifier 2.

2. 发明专利

JPH10243338A VIDEO RECORDING SYSTEM 失效
公开(公告)号：JPH10243338A
公开(公告)日：1998-09-11
申请号：JP4226897
申请日：1997-02-26
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK
发明人： TAKEBUCHI KENJI , KANESHIRO KATSUMI , KURIHARA TAKASHI , ICHIKAWA YOSHIHISA
IPC分类号： H04N5/91
摘要： PROBLEM TO BE SOLVED: To inhibit normal recording of a video signal processed by a copy prevention device and to secure normal recording of a video signal not processed by the copy prevention device excluding the malfunction of copy guard by detecting a peak level only in a specific period for superposing a copy guard signal to the video signal. SOLUTION: A peak value type AGC circuit 11 detects a peak level obtained immediately after temporarily allowing the instantaneous level of a video signal Vs2 of which period pulse top is DC clamped to a reference level VCL to fall to the reference level VCL and restricts the amplitude of the video signal Vs2 so that the peak level is less than the prescribed limit level V1 of the reference level VCL. A recording circuit 23 records the video signal of which amplitude is limited by the AGC circuit 11 in a recording medium. A timing control means allows the AGC circuit 11 to detect the peak level only to a specific period for superposing a copy guard signal to the video signal Vs2.

3. 发明专利

JPS60123111A AMPLIFIYING CIRCUIT 失效
公开(公告)号：JPS60123111A
公开(公告)日：1985-07-01
申请号：JP22992683
申请日：1983-12-07
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： ICHIKAWA YOSHIHISA , SATOU TETSUO
IPC分类号： H03F1/00
摘要： PURPOSE:To prevent the occurrence of pop tone at a power-off time by driving an amplifying circuit with a reference voltage whose level falls in accordance with level fall of a power source voltage at the power-off time and reducing the level of an output voltage quickly. CONSTITUTION:When a power switch S1 is turned on to supply a power source voltage +VCC, a base voltage VC is supplied to a transistor TRQ11 to turn on this TR, and a current I1 is flowed to a resistance R14, And a TRQ13 is turned on, and a voltage VA of capacitor C1 rises. When the switch S1 is turned off, the voltage VC falls by the time constant of a filter F1. Since the TRQ13 continues to be in the turn-on state, the electric charge of the capacitor C1 is discharged through a resistance R15, and the voltage VA falls. Then, an output voltage VQ of a differential amplifier to which the voltage VA is supplied as the reference voltage is reduced gradually.

4. 发明专利

JPS59148409A Amplifier 失效
标题翻译：放大器
公开(公告)号：JPS59148409A
公开(公告)日：1984-08-25
申请号：JP2158983
申请日：1983-02-14
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： SATOU TETSUO , ICHIKAWA YOSHIHISA
IPC分类号： H03F1/00
摘要： PURPOSE: To attain surely silencing operation with electronic circuit constitution by grounding an output of an amplifier in terms of AC before a transistor(TR) in the amplifier is driven into a saturated region after the interruption of power supply.
CONSTITUTION: When the power supply is interrupted, a power supply voltage +V
cc is decreased comparatively rapidly, but the potential at a common connecting point of bias resistors R
1 , R
2 is decreased slowly because a capacitor C
4 for power supply ripple elimination is connected to the connecting point. On the other hand, a potential at a terminal 2 (output terminal of amplifier) is made almost equal to that at a terminal 5 by negative feedback via resistors R
4 , R
5 . As a result, when the difference of potentials at terminals 2 and 3 reaches a prescribed value, a TRQ
11 is turned on, a base current flows to a TRQ
12 and the TRQ
12 is turned on. Thus, the rapid current change in an output signal being a cause to the generation of pop tone flows to ground via a capacitor C
3 .
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过在放大器的晶体管（TR）在电源中断之后将晶体管（TR）驱动到饱和区域之前，通过将放大器的输出端接地来实现电子电路结构的可靠的消音操作。构成：当电源中断时，电源电压+ Vcc相对较快地降低，但是偏置电阻R1，R2的共同连接点的电位缓慢下降，因为用于电源纹波消除的电容器C4连接到连接点。另一方面，端子2（放大器的输出端子）的电位与端子5的电位大致相等，通过电阻R4，R5的负反馈。结果，当端子2和3的电位差达到规定值时，TRQ11导通，基极电流流向TRQ12，TRQ12导通。因此，作为产生流氓音的原因的输出信号的快速电流变化经由电容器C3流到地。

5. 发明专利

JPH10257522A SIGNAL PROCESSING CIRCUIT FOR VTR 失效
公开(公告)号：JPH10257522A
公开(公告)日：1998-09-25
申请号：JP7262097
申请日：1997-03-10
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK , VICTOR COMPANY OF JAPAN
发明人： KURIHARA TAKASHI , ICHIKAWA YOSHIHISA , ARAI IZUMI , KURABAYASHI NAOKI , KURAMOTO HIROSHI , MUROTANI TAKESHI
IPC分类号： G11B5/027 , G11B20/02 , H03D7/16 , H04N9/79 , H04N9/793 , H04N9/83 , H04N9/84
摘要： PROBLEM TO BE SOLVED: To stably enable crosstalk removing operation even at the time of shifting into special reduction by providing a clock generating circuit for generating a clock signal synchronized with a horizontal synchronizing signal separated from a regenerative brightness signal. SOLUTION: In the case of NTSC system, a color under signal is delayed by a CCD 3 as a delay element for one horizontal period, supplied to a 2nd frequency converting circuit (main converter) 2 and turned into standard color signal. The clock signal to be used for the delay operation of CCD 3 is formed by a clock signal generating circuit 22. When signals outputted from 1st and 2nd frequency converting circuits 1 and 2 are in-phase, at an arithmetic circuit 4, a double crosstalk component is extracted by subtraction, that component is attenuated just for -6dB, namely, leveled down into 1/2, a crosstalk component is recovered and that component is attenuated from one covered output signal so that the crosstalk component contained in such a converted output signal can be removed.

6. 发明专利

JPS6282751A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS6282751A
公开(公告)日：1987-04-16
申请号：JP22183185
申请日：1985-10-07
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： ICHIKAWA YOSHIHISA , KURIHARA TERUMI , TAKESHITA RITSUJI
IPC分类号： H04M1/64 , H03F1/00 , H03G3/00 , H03G3/02
摘要： PURPOSE:To reduce noise and power consumption by providing an output circuit respectively to the final stage of plural signal transmission paths and providing a standby circuit controlling the current of each output circuit. CONSTITUTION:The output circuits 62-69 are provided respectively to the final stage of plural signal transmission paths and muting circuits 52-54 are provided respectively to each output circuit. Then a mute control signal is fed from an external connection terminal of an IC 1 synchronously with the changeover of switches S1-S4 provided to plural signal transmission paths in the muting circuit and each output is made inoperative tentatively at the changeover of the switches to reduce generation of pop noise attended with the changeover of switches. When the amplifier circuit 1 is inoperative, a minute idling current flows to each output circuit and a standby circuit 100 supplying a desired current at operation is provided to drive the amplifier circuit at a low power consumption.

7. 发明专利

JPS6282750A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS6282750A
公开(公告)日：1987-04-16
申请号：JP22183085
申请日：1985-10-07
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： ICHIKAWA YOSHIHISA , KURIHARA TERUMI , TAKESHITA RITSUJI
IPC分类号： H04M1/64 , H03F1/00 , H03G3/00 , H03G3/02
摘要： PURPOSE:To decrease a noise signal attended with the changeover of a switch provided to plural signal transmission paths by applying a muting control signal from an external connection terminal of a semiconductor integrated circuit so as to make each output circuit inoperative at the same time. CONSTITUTION:A mute signal Vm is fed to a terminal 18 from a CPU 3 nearly synchronously with the changeover of a switch circuit by the CPU 3. Then a mute control circuit 51 is driven at a time tw to give a mute signal Vm' to mute circuits 52-54, then the output circuits 62-64 are make inoperative temporarily at the same time. The time width is nearly equal to the time width tw of the mute control signal Vm and larger than the generated time width of a noise signal. Thus, even when the noise signal is generated in any signal path depending on the changeover of switches S1-S4, since the output circuit being the final stage is made inoperative temporarily, unpleasant pop noise to a listener is reduced or prevented.

8. 发明专利

JPS61269519A TWO-WAY SWITCH CIRCUIT 失效
公开(公告)号：JPS61269519A
公开(公告)日：1986-11-28
申请号：JP11046685
申请日：1985-05-24
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： ICHIKAWA YOSHIHISA , KURIHARA TERUMI , SATO TETSUO
IPC分类号： G11B5/027 , H03K17/76
摘要： PURPOSE:To decrease generation of distortion at signal transmission by providing a diode bridge composing of a bipolar transistor (TR) and a switch circuit so as to incorporate them with other electronic circuit for circuit integration. CONSTITUTION:Diode bridges 1, 2 composing of TRs Q1-Q4, Q1'-Q4' of diode connection are provided to the two-way switch circuit and a control circuit 3 controls the bridges 1, 2 at recording. A voice signal from a microphone MIC is fed to the bridge 1 via amplifiers 4, 5 while being converted into a current (i) and an output current i' from the bridge 1 is fed to a recording/ reproducing head 6. Further, the current (i) from the head 6 is fed to the bridge 2 at signal reproduction and the output current i' from the bridge 2 is fed to a speaker SP via amplifiers 11, 12. Then the bridges 1, 2 and the control circuit 3 are incorporated in the IC circuit together with other amplifiers 4, 5, 11, 12 to decrease generation of distortion at signal transmission.

9. 发明专利

JPH10276394A VIDEO SIGNAL RECORDING CIRCUIT 失效
公开(公告)号：JPH10276394A
公开(公告)日：1998-10-13
申请号：JP7600697
申请日：1997-03-27
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK , HITACHI VIDEO IND INF SYST INC
发明人： TAKEBUCHI KENJI , KANESHIRO KATSUMI , ICHIKAWA YOSHIHISA , ICHIKAWA KATSUMI , TABATA AKIFUMI , KUNITAKE HIROYUKI
IPC分类号： H04N5/91
摘要： PROBLEM TO BE SOLVED: To record the amplitude and level of entire video signal while exactly adjusting them into specified level when recording an additional signal while superimposing it by providing a signal superimposing circuit for superimposing the additional signal at the specified level on the video signal before frequency modulation processing based on a control signal from the outside. SOLUTION: A video signal recording and reproducing integrated circuit device 1 forms the main circuit section of VTR, and a recording system circuit 100 and a reproducing system circuit 200 are formed while being integrated on the same semiconductor substrate. A signal superimposing circuit 110 at this recording system circuit 100 superimposes the additional signal at the specified level on the video signal, which is amplitude-controlled and level-controlled by an AGC circuit 104 and a synchronizing clamp circuit 108, based on a superimpose control signal Sc1 from the outside. The superimpose control signal Sc1 is generated based on the plotting information of characters or the like by an external signal superimpose control circuit 402 and arbitrarily inputted through an external terminal P1 at the integrated circuit device 1.

10. 发明专利

JPH0787456A VIDEO SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH0787456A
公开(公告)日：1995-03-31
申请号：JP18680093
申请日：1993-06-30
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST , HITACHI MICOM SYST KK
发明人： WATANABE KATSUYUKI , TABATA AKIFUMI , ICHIKAWA YOSHIHISA , ARAI IZUMI
IPC分类号： G11B20/06 , H04N5/21 , H04N5/93
摘要： PURPOSE:To provide a video signal processing circuit from which a stable video signal is obtained by preventing malfunction of gate clamp and malfunction of a synchronizing separator circuit due to noise produced in the special reproduction mode of a VTR. CONSTITUTION:The operation of a gate clamp circuit 8 arranged in the output stage of a nonlinear de-emphasis circuit 7 is stops for a noise period detected by an envelope detection circuit 14. Furthermore, a clip circuit 16 is provided in the input stage of a synchronizing separator circuit 12 to clip level of a synchronizing signal tip or below. Through the constitution above, the gate clamp circuit 8 stops for the noise period and makes a signal stable for the noise period and just after noise period. Thus, a stable synchronizing signal is obtained and the disturbance in a vertical synchronizing signal or skew or the like on a monitor television screen is prevented.

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