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1. 发明专利

JP2003258130A MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003258130A
公开(公告)日：2003-09-12
申请号：JP2002057708
申请日：2002-03-04
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SUZUKI SHINOBU , ADACHI TETSUO , TAKEUCHI TAKASHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To restrain the deterioration of write speed of a flash memory by suppressing bird's beak generated in an interlayer film interposed between a floating gate and a control gate for a memory cell. SOLUTION: The interlayer film 4, interposed between a conductor film 3 for the floating gate and a conductor film 5 for the control gate, is constituted of a superposed film, having 4-layered structure consisting of a silicon nitride film 4a arranged at the lowermost layer, a silicon oxide film 4b, a silicon nitride film 4c and a silicon oxide film 4d. According to this method, the bird's beak of the silicon oxide film constituting one part of the interlayer film 4 can be suppressed, whereby deterioration of capacity of the interlayer film 4 can be restrained and a structure, capable of suppressing the deterioration of the writing speed, can be obtained. COPYRIGHT: (C)2003,JPO

2. 发明专利

JPH08279566A PARALLEL-CONNECTED TYPE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND USE OF SAID DEVICE 失效
公开(公告)号：JPH08279566A
公开(公告)日：1996-10-22
申请号：JP8100395
申请日：1995-04-06
申请人： HITACHI LTD
发明人： KATO MASATAKA , ADACHI TETSUO , KUME HITOSHI , KOBAYASHI TAKASHI
IPC分类号： G11C17/00 , G11C5/14 , G11C16/04 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/06
摘要： PURPOSE: To realize a high-density writable nonvolatile storage device by a method wherein MOS transistors, which respectively have each one of drain regions and source regions, which are formed in a well layer, are used as memory cells. CONSTITUTION: An N-type well layer 11 and a P-type well layer 12 are formed inn order on the upper layer part of a semiconductor substrate 10 consisting of a P-type silicon film and drain and source regions 7 and 8 are formed in the interior of the layer 12. A gate insulating film 1 is formed on the surface of the layer 12 and floating gate 2 consisting of a metal film, such as a polycrystalline silicon film or a tungsten film, are formed on the film 1. The surfaces of the gates 2 are covered with an interlayer insulating film 3 consisting of a silicon oxide film and a word line 4 consisting of a metal film, such as a polycrystalline silicon film or a tungsten film, is formed on the film 3. Memory cells are electrically insulated from each other by each coil isolation region 5. As the memory cells are parallel-connected, the readout of data can be conducted at high speed.

3. 发明专利

JPH08181231A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08181231A
公开(公告)日：1996-07-12
申请号：JP32441494
申请日：1994-12-27
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： ADACHI TETSUO , KATO MASATAKA , KOBAYASHI TAKASHI , MORIMOTO TADAO , MIYAMOTO NAOKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE: To provide a nonvolatile semiconductor storage device, in which charge holding characteristics are improved and which has high reliability, and manufacture thereof. CONSTITUTION: In a nonvolatile semiconductor storage device with a floating gate electrode 4 formed on a semiconductor substrate 1 through a gate insulating film 3 and a control gate electrode 6 formed onto the upper section of the gate electrode 4 through an inter-layer insulating film 5, a process, in which the floating gate electrode is shaped, a process in which the upper end sections of the floating gate electrode are rounded, and a process in which the inter-layer insulating film is formed, are contained. Accordingly, field concentration in the inter-layer insulating film can be prevented and isolation voltage and distubance resistance are not lowered by forming the upper end sections of the floating gate electrode in an arcuate shape, thus thinning the inter-layer insulating film, then realizing the large nonvolatile semiconductor storage device.

4. 发明专利

JPH0677437A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH0677437A
公开(公告)日：1994-03-18
申请号：JP33140392
申请日：1992-12-11
申请人： HITACHI LTD
发明人： KATO MASATAKA , ADACHI TETSUO , TANAKA TOSHIHIRO , SASAKI TOSHIO , KUME HITOSHI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To operate at high speed with low consumption power and to reduce an effective cell area in a title device which is programmable electrically. CONSTITUTION:In an electrically programmable nonvolatile semiconductor memory device comprising a memory cell array where a plurality of memory cells consisting of MOSFETs having floating gate electrode 3 are laid out in a matrix, for wiring operation, positive voltage is impressed on an n-type drain region 7 and negative voltage on a control gate 5, and a source region 6 is grounded; for erase operation, positive voltage is impressed on the control gate 5, and all the other electrode and a semiconductor substrate 1 are grounded. This design can suppress consumption power because of both operations of write and erase by use of tunnel phenomena. Drain voltage during data write can be reduced by use of negative voltage for a word line, so that a deterioration in the gate oxide film in a channel zone during data programming can be relived.

5. 发明专利

JPH03228372A SEMICONDUCTOR NONVOLATILE MEMORY 失效
公开(公告)号：JPH03228372A
公开(公告)日：1991-10-09
申请号：JP2196290
申请日：1990-02-02
申请人： HITACHI LTD
发明人： ADACHI TETSUO , SEKI KOICHI , KUME HITOSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To suppress generation of hot holes with a channel current as a seed by respectively providing changeover switch elements in drain regions (source regions) of memory cells, and isolating the respective cells from a data line at the time of erasing. CONSTITUTION:A switch element QS1 is conducted, and a switch element QS2 is not conducted at the time of erasing. A ground potential VSS such as 0V is applied to a word line WL and a data line DL. In this case, a drain region is connected with a diode element DD reversely to be electrically opened from a drain side. Thus, regarding a parasitic electrostatic capacitance, it is scarcely affected by an other drain diffused layer capacitance 11b, the wiring capacitance 11a of the data line, and only the capacitance 11b is in a connected state in each cell when erasing operation takes place. Therefore, the capacitance 11b is charged by a micro channel current, and its drain potential is abruptly raised. This 'potential rise is operated in a direction for reducing the channel current, thereby suppressing generation of hot holes to a sufficiently low level.

6. 发明专利

JPH0284776A MANUFACTURE OF FLOATING GATE TYPE NONVOLATILE MEMORY 失效
公开(公告)号：JPH0284776A
公开(公告)日：1990-03-26
申请号：JP27581587
申请日：1987-11-02
申请人： HITACHI LTD
发明人： ADACHI TETSUO , YAMAMOTO HIDEAKI , KUME HITOSHI , TSUKADA TOSHIHISA , HIRAIWA ATSUSHI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent the film quality of a gate oxide film from deteriorating by plasma damage and to obtain a nonvolatile memory, which is suitable for an increase in integration using an O-N-O film as an interlayer insulating film and has a high efficiency, by a method wherein an N-O-N-O film is formed on a floating gate and after a gate insulating film is formed, the uppermost Si3N4 film is removed to form the O-N-O film. CONSTITUTION:A floating gate electrode 2 consisting of a first conductor substance film is formed on a P-type semiconductor substrate 1 through a first gate insulating film 3 and an SiO2 film, an Si3N4 film, an SiO2 film and an Si3N4 film 8, which are used as a second insulating film 5, are adhered in this order on the whole surface of the electrode 2. Then, a photoresist 9 on a peripheral MOS region is worked into a desired pattern by a photoetching process and the Si3N4 film 8, the SiO2 film, the Si3N4 film and the SiO2 film 5 are removed from top using the patterned resist 9 as a mask. Then, after the resist 9 is removed, a peripheral MOS gate oxide film 4 is formed. After that, the Si3N4 film 8 on the film 5 is removed, a second conductor substance film 6 is formed on the whole surface and a control gate electrode 10 and a peripheral MOS gate electrode 11 are formed.

7. 发明专利

JPH1064285A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH1064285A
公开(公告)日：1998-03-06
申请号：JP21828196
申请日：1996-08-20
申请人： HITACHI LTD
发明人： KATO MASATAKA , TSUCHIYA OSAMU , YADORI SHOJI , TANAKA TOSHIHIRO , ADACHI TETSUO
IPC分类号： G11C17/00 , G11C7/00 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To make possible the application of a micro memory cell and reduce an area of a memory chip, by impressing a voltage to a source, a drain diffusion layer step by step when electrons are pulled from a floating gate electrode. SOLUTION: When electrons are pulled out from a floating gate electrode, a positive voltage is impressed to a diffusion layer opposite to a diffusion layer where the electrons are to be pulled, thereby to decrease a maximum voltage impressed between a source terminal and a drain terminal. Further, a positive voltage is impressed to a control gate electrode of a memory cell where the electrons are not pulled and a diffusion layer not in a pull-out direction is let to float. A write/erasure method for the memory cell which is not restricted by a voltage decrease inviting a problematic punch-through current between the source and drain when the memory cell is microminiaturized, in other words, not restricted by a decrease of a punch-through voltage is obtained, and a memory chip can be very small.

8. 发明专利

JPH09153559A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, ITS OPERATING METHOD, AND ELECTRONIC CIRCUIT DEVICE 失效
公开(公告)号：JPH09153559A
公开(公告)日：1997-06-10
申请号：JP31379895
申请日：1995-12-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TSUJIKAWA TETSUYA , TANAKA TOSHIHIRO , KANEMITSU MICHITARO , KATO MASATAKA , ADACHI TETSUO
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent the phenomenon of hot electron in a given memory cell when a charge accumulated in source and drain regions is reset after write and erase operation at a memory cell in a non-volatile memory. SOLUTION: A memory cell in a memory block MB is turned off just after write or erase operation is carried out in the given memory block of a flash memory. Then, potential of a main bit line BL is reduced to a grounding level, and switching MOSFET's Q1S and Q2s are turned on. As a result, a charge accumulated in a sub-source line SS and a sub-bit line BLS is each discharged to a grounding potential VSS or the main bit line BL.

9. 发明专利

JPH04186768A MANUFACTURE OF NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04186768A
公开(公告)日：1992-07-03
申请号：JP31398390
申请日：1990-11-21
申请人： HITACHI LTD
发明人： KUME HITOSHI , ADACHI TETSUO , OJI YUZURU , KURE TOKUO , USHIYAMA MASAHIRO , KAWAKAMI HIROSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To form a nonvolatile memory transistor of a 2-layer gate electrode structure on the same semiconductor substrate as that of a MOS transistor for a peripheral circuit for driving it by forming an interlayer insulating film by using a film forming technique by a chemical vapor depositing method. CONSTITUTION:A substrate 1 of a region for forming a MOS transistor for a peripheral circuit is covered entirely with a first layer conductive layer 5. After an interlayer insulating film 6 is formed, a second conductive layer 7 is continuously formed thereon. The layer 7, the film 6 and the layer 6 of a region for forming the MOB transistor for the peripheral circuit are sequentially removed. The semiconductor substrate surface of the removed region is newly thermally oxidized, a gate oxide film 8 of the MOS transistor for the peripheral circuit is formed, and then a third conductive layer 10 is continuously formed. The layer 10 is processed to form a single layer gate electrode of the MOS transistor, and then the layers 7, 6 and a first conductive layer 15 are superposed to be cut to form a 2-layer gate electrode of a nonvolatile memory transistor.

10. 发明专利

JPH0278276A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0278276A
公开(公告)日：1990-03-19
申请号：JP22867988
申请日：1988-09-14
申请人： HITACHI LTD
发明人： KUME HITOSHI , ADACHI TETSUO , KAMIGAKI YOSHIAKI , TSUKADA TOSHIHISA , KOMORI KAZUHIRO , NISHIMOTO TOSHIAKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To obtain an electrically re-writable non-volatile memory cell optimized in a writing and all erasing property by a method wherein a floating gate is provided to two positions on a drain region side and a source region side, which are connected to each other into one piece in an element isolating region. CONSTITUTION:A memory cell is composed of the following: a thick first gate oxide film 4; a thin first gate oxide film 5; a second gate oxide film whose thickness is nearly equal to that of the the oxide film 4; floating gate electrodes 6 on the oxide films 4 and 5; a control gate electrode 9 on the oxide film 7 and the electrode 6; an interlaminar oxide film 8; an n -type semiconductor region 11 of a source region; a p -type semiconductor region 13 covering the region 11; an n -type semiconductor region 1; and an n type semiconductor region 14. In this constitution, two of the electrodes 6 are connected to each other into one piece in an element isolating region. By this setup, charges written from the drain region 11 into the electrode 6 are extracted toward the source region 12 or written charges can be erased out, so that a wiring and a erasing property can be optimized independently of each other.

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