会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明专利
    • Resolver/digital converter and control system using resolver/digital converter
    • 使用分辨率/数字转换器的分辨率/数字转换器和控制系统
    • JP2007263943A
    • 2007-10-11
    • JP2006307317
    • 2006-11-14
    • Hitachi Ltd株式会社日立製作所
    • KANEKAWA NOBUYASUSASAKI SHOJIABE YOSHITAKA
    • G01D5/245G01D5/244H02P6/12
    • H03M1/1004H03M1/1019H03M1/108H03M1/645
    • PROBLEM TO BE SOLVED: To provide a resolver/digital converter, having a function for self-detecting a failure without interrupting the normal operation. SOLUTION: The resolver/digital converter is provided with a normal operation function; a temperature characteristic identifying function; a first temperature characteristic correcting function for correcting an estimated angular output from the normal operation function based on a temperature characteristic identification value, obtained by the temperature characteristic identifying function; a holding function for holding the temperature characteristic identification value (1); and a second temperature characteristic correcting the function for correcting the estimated angular output from the temperature characteristic identifying function, based on the temperature characteristic identification value obtained by the temperature characteristic identifying function and held by the holding function (2). COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供一种具有自动检测故障而不中断正常操作的功能的解算器/数字转换器。 解决方案:解算器/数字转换器具有正常的操作功能; 温度特性识别功能; 第一温度特性校正功能,用于基于通过温度特性识别功能获得的温度特性识别值来校正来自正常操作功能的估计角度输出; 保持温度特性识别值(1)的保持功能; 以及基于由温度特性识别功能获得并由保持功能(2)保持的温度特性识别值,校正来自温度特性识别功能的估计角度输出的功能的第二温度特性。 版权所有(C)2008,JPO&INPIT
    • 7. 发明专利
    • Level generation circuit
    • 电平生成电路
    • JP2012209762A
    • 2012-10-25
    • JP2011073874
    • 2011-03-30
    • Hitachi Ltd株式会社日立製作所
    • NAKAYAMA AKIRAYOSHINAGA MAKIABE YOSHITAKAHIRAYAMA NORIFUMIHAYASHI MASAHIRO
    • H03K19/00
    • G05F3/20
    • PROBLEM TO BE SOLVED: To dispense with an external power supply for generating a gate voltage for a MOSFET operating with a grounded gate for protecting a low voltage MOSFET.SOLUTION: A level generation circuit includes: a constant current generation section for generating a first current of a constant magnitude from a first supply voltage; a first current mirror circuit section comprising a first thin film NMOSFET and a second thin film NMOSFET and outputting a second current proportional to the first current; a protection circuit section comprising a third thin film NMOSFET and a first thick film PMOSFET used with a grounded gate for protecting the second thin film NMOSFET, a first diode for preventing a backflow of current to the first power supply, and a second diode for preventing a gate-source voltage of the third thin film NMOSFET from becoming negative; a second current mirror circuit section for outputting a third current proportional to the second current; and a first Zener diode section for generating a first constant voltage from the third current.
    • 要解决的问题:省去用于产生用于保护低压MOSFET的接地栅极操作的MOSFET的栅极电压的外部电源。 解决方案:电平发生电路包括:恒定电流产生部分,用于从第一电源电压产生恒定幅度的第一电流; 第一电流镜电路部分,包括第一薄膜NMOSFET和第二薄膜NMOSFET,并输出与第一电流成比例的第二电流; 保护电路部分,包括第三薄膜NMOSFET和用于保护第二薄膜NMOSFET的接地栅极的第一厚膜PMOSFET,用于防止电流回流到第一电源的第一二极管和用于防止 第三薄膜NMOSFET的栅源电压变为负值; 第二电流镜电路部分,用于输出与第二电流成比例的第三电流; 以及第一齐纳二极管部分,用于从第三电流产生第一恒定电压。 版权所有(C)2013,JPO&INPIT
    • 10. 发明专利
    • SEMICONDUCTOR INTEGRATED CIRCUIT
    • JP2000055992A
    • 2000-02-25
    • JP22222298
    • 1998-08-06
    • HITACHI LTD
    • KITA MASAHITOABE YOSHITAKA
    • G01R31/316G01R31/28
    • PROBLEM TO BE SOLVED: To shorten device test time concerning the threshold of a semiconductor integrated circuit using a reference voltage as a threshold of circuit characteristic. SOLUTION: To a semiconductor integrated circuit having a first circuit 3 using a reference voltage selected via a feedback loop as a threshold of circuit characteristic and a second circuit 4 capable of outputting the result of operation executed differently from the first circuit by way of output switches S8 to S12 from a buffer circuit 40 to an external terminal 41, a monitor switch S7 selectively conducting the reference voltage selected in the first circuit is provided. Synchronizing with the on state monitor switch S7, the selected state of the reference voltage by the first circuit can be determined corresponding to the state of the first external input terminals 34 and 45 of the first circuit and the second circuit output switch is controlled to off state.