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1. 发明专利

JPH0198297A ELECTRONIC DEVICE BODY 失效
公开(公告)号：JPH0198297A
公开(公告)日：1989-04-17
申请号：JP25455387
申请日：1987-10-12
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： WATANABE HIROSHI , TAKAHASHI YOSHIAKI , SAKATA MASAYUKI , ADACHI KOSHIRO , IDE TOSHIYUKI , YOSHIDA MITSUO
IPC分类号： G10K11/16 , H05K7/20
摘要： PURPOSE:To reduce noise which is generated by air intake speed and an air blasting fan by providing a circular arc inlet in which recesses are formed in the inner part of a body in the center part of the front and rear face of the body. CONSTITUTION:An electronic device body has an air inlet 2 in the center thereof, heating parts are housed in the right and left body 1, and switches and input and output devices are incorporated in a console housed part 19 for an operator. Further, the air inlet 2 are arranged approximately in the center part of an outer face panel 4 of the body 1, slits 6 are radially arranged from the center of the air inlet and take-in cooling wind is divided into the right and left without resistance in the body. Therefore, intake wind velocity is reduced approximately 20-30% as compared with the flat shape by changing the intake shape to the circular arc and noise direct sound is decreased to about a half.

2. 发明专利

JPH02210852A HIGH-FREQUENCY VIDEO AMPLIFIER 失效
公开(公告)号：JPH02210852A
公开(公告)日：1990-08-22
申请号：JP2982389
申请日：1989-02-10
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： SASE TAKASHI , SATO HIDEO , KATO KAZUO , KAMATA YASUHARU , IDE TOSHIYUKI , KOBAYASHI KUNIO
IPC分类号： H01L23/15 , H01L23/14 , H05K9/00
摘要： PURPOSE:To make it possible to obtain the high-frequency characteristics and low thermal resistance of the title amplifier by a method wherein a power transistor chip and a bipolar bare chip are mounted on an Al nitride substrate and a through hole is provided for a feed. CONSTITUTION:A circuit wiring conductor pattern 20 is formed on the upper surface of an Al nitride substrate 10 and chip components 30 to 33 are mounted, while the lower surface of the substrate 10 is used as a solid grounding surface 21. Moreover, the connection between the upper surface conductor pattern 20 and the lower surface conductor pattern 21 is performed through a through hole 22. Here, as the thermal expansion coefficient of the substrate 10 is near that of Si, the adhesion of the substrate 10 with the power transistor chip 32 and the bipolar bare chip 33 is easy, the chips 32 and 33 can be mounted in a small size and the dielectric constant and dielectric loss of the substrate 10 are low. Moreover, as the substrate 10 has a high thermal conductivity, the chip 32 is superior in heat dissipation. Thereby, a high-frequency video amplifier is superior in high-frequency characteristics and the thermal resistance of the amplifier can be made small.

3. 发明专利

JPH01138796A COOLING AND VENTILATING STRUCTURE OF CASE FOR CONTAINING ELECTRONIC APPARATUS 失效
公开(公告)号：JPH01138796A
公开(公告)日：1989-05-31
申请号：JP29597487
申请日：1987-11-26
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： WATANABE HIROSHI , TAKAHASHI YOSHIAKI , SAKATA MASAYUKI , IDE TOSHIYUKI
IPC分类号： H05K7/20
摘要： PURPOSE:To ventilate a highly dense electronic apparatus, which is large in heat release and sensitive to the dust, with a clean air by a method wherein a cooling air from a lower intake vent rises through a low heat release element packaging section and exhausted, on the other hand a cooling air from an upper intake vent rises through a high heat release element packaging section and exhausted. CONSTITUTION:Floating dust, whose diameter is equal to or larger than 1mu, in the air is a precipitable dust and floating within the space 30-40cm thick above the floor. Therefore, a lower intake airflow 7 is comparatively inclined to take in the dust, but the air flow 7 is used to cool a low heat release element, so that it does not harm to the element for practical use and is warmed up cooling the element and rises up through due to a natural convention. And, a high heat release and highly dense element, which is sensitive to the effect of the dust, is cooled by an upper intake airflow 8 through a blower fun, a clean air containing a small amount of dust is drawn in as the airflow 8 shown by an arrow A, then descends as shown by an arrow B, turns to the direction shown by an arrow C, and then rises up as shown by an arrow D.

4. 发明专利

JPH03204258A FAULT DETECTION SYSTEM, TRANSMISSION LINE RECONSTITUTION SYSTEM AND COMMUNICATION SYSTEM 失效
公开(公告)号：JPH03204258A
公开(公告)日：1991-09-05
申请号：JP34471789
申请日：1989-12-30
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： MARUYAMA HISAYUKI , IDE TOSHIYUKI , YASUMOTO SEIICHI , MIZOKAWA SADAO , ONUKI TAKESHI , ISHIHARA TOSHIO , SATAKE MASAHITO , UCHIYAMA TOSHIHIKO
IPC分类号： G06F11/00 , H04L12/42 , H04L12/437
摘要： PURPOSE:To make a high speed detection to a fault with high possibility in the normal operating state by executing sequentially a fault detection means in the order of seeking a cause to a fault at a higher speed till the cause to the fault is detected. CONSTITUTION:When transmission lines 21, 22 are normal, a data is sent through any of them and a monitor signal is sent to the other transmission line as a standby transmission line and when the transmission lines are in loopback state, the data is sent through both the transmission lines. That is, signal detectors(DET) 27, 31 receive a special control signal of 'invitation' or a special control signal 'monopoly' or a monitor signal from the data frame during data transmission. Since it is in the case of occurrence of a fault in a transmission line receiving a monitor station(ST) or an ST located at an upperstream to the transmission line when no signal is received, that is, in the state of no signal, and when DETs 27, 31 of the ST detects a no signal state, the ST enters the transmission line reconstitution operation. Thus, high speed detection is attained.

5. 发明专利

JPH01161942A DATA TRANSMISSION EQUIPMENT AND ITS METHOD 失效
公开(公告)号：JPH01161942A
公开(公告)日：1989-06-26
申请号：JP31888387
申请日：1987-12-18
申请人： HITACHI LTD
发明人： NISHIKAWA ATSUHIKO , WATANABE HIROSHI , TAKAHASHI YOSHIAKI , IDE TOSHIYUKI
IPC分类号： H04L12/40
摘要： PURPOSE:To suppress data transfer between unintended modules by suppressing bus open in a slave module even if the access of a master module is interrupted during the data transfer between the master module and the slave module made access. CONSTITUTION:A bus busy 4 is set to a means representing the occupancy of a data bus 9 till a replay signal 7 from slave modules 31-33 made access by master modules 21-23 receiving a bus occupancy permission signal 6 is fetched. Furthermore, the bus busy signal 4 is set even from the slave module made access during data transfer. Thus, the bus occupancy permission signal 6 is not issued to other master modules. Then even if the master module is on the way of data transfer and interrupts accessing, the succeeding bus operation is applied normally.

6. 发明专利

JPS58184680A Vector arithmetic processor 失效
标题翻译：矢量算术处理器
公开(公告)号：JPS58184680A
公开(公告)日：1983-10-28
申请号：JP6741482
申请日：1982-04-23
申请人： Hitachi Ltd
发明人： ABE SHIGEO , BANDOU TADAAKI , HIRASAWA KOUTAROU , IDE TOSHIYUKI
IPC分类号： G06F15/16 , G06F15/167 , G06F15/78 , G06F15/80 , G06F17/16
CPC分类号： G06F15/8053
摘要： PURPOSE:To facilitate microprogramming for even vector arithmetic dealing with many variables, by supporting the storage and fetch of a write address with a first-in first-out (FIFO) buffer. CONSTITUTION:A vector arithmetic processor consists of an address arithmetic unit 100, memory units 200 and 300, and arithmetic unit 400. When data read out of a memory 310 is processed and returned to its original address every time vector arithmetic is carried out, read addresses are inputted successively to the FIFO buffer 370 and every time one arithmetic result is outputted, corresponding addresses are read out of the FIFO buffer 30 synchronously and set in an address register 350 for memory writing.
摘要翻译：目的：为了促进处理许多变量的偶数矢量运算的微程序，通过支持使用先进先出（FIFO）缓冲区来存储和读取写入地址。构成：矢量运算处理器包括地址运算单元100，存储单元200和300以及运算单元400.当每次执行矢量运算时，读出存储器310的数据被处理并返回到其原始地址，读取地址被连续地输入到FIFO缓冲器370，并且每当输出一个运算结果时，对应的地址从FIFO缓冲器30同步地读出并设置在用于存储器写入的地址寄存器350中。

7. 发明专利

JPS5864688A DATA PROCESSOR 失效
公开(公告)号：JPS5864688A
公开(公告)日：1983-04-18
申请号：JP16268781
申请日：1981-10-14
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： BANDOU TADAAKI , FUKUNAGA YASUSHI , HIRAOKA YOSHINARI , MATSUMOTO HIDEKAZU , KAWAKAMI TETSUYA , IDE TOSHIYUKI , KATOU TAKESHI
IPC分类号： G06F12/10 , G06F12/08 , G06F15/16 , G06F15/177
摘要： PURPOSE:To control a cash memory without contradiction in case of the occurrence of a cash error, by accessing a main memory owing to the cash error after setting a significance display part of the cash memory. CONSTITUTION:To a memory controller 12 connected to a main storage device 10, a job processor 40 which accesses the memory on the basis of a virtual address for the execution of a instructions is connected, and the processor 40 is provided with cash memories 41 and 42 accessed on the basis of virtual addresses. Then, the controller 12 clears the significance display part of a data block corresponding to a virtual address if a page fault occurs during read access to the device 10. If a page fault occurs during write access the significance display part of a corresponding data block is cleared when the block is in a corresponding cash memory.

8. 发明专利

JPS5835643A DATA PROCESSING DEVICE FOR ERROR DETECTION OF UNDEFINED LENGTH INSTRUCTION 失效
公开(公告)号：JPS5835643A
公开(公告)日：1983-03-02
申请号：JP13271781
申请日：1981-08-26
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： FUKUNAGA YASUSHI , BANDOU TADAAKI , HIRAOKA YOSHINARI , HIRASAWA KOUTAROU , MATSUMOTO HIDEKAZU , IDE TOSHIYUKI , KATOU TAKESHI , NAKANISHI HIROAKI , KAWAKAMI TETSUYA
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F11/08
摘要： PURPOSE:To improve the capability of error detection for undefined length instructions, by detecting errors on a basis of contents of the end flag, which is added to an operand designator, and the number of operands. CONSTITUTION:When an end flag E of an operand inputted to a decode processing end byte number detector 65 is (1), an output gate 301 is opened, and the number of bytes OSB of the operand designator on a bus 215 is outputted to a bus 214. In this case, unless a stop bit S of the operand designator is (1), it means that the number of operand designator is larger than the number of operands, and this is detected as an error. Then, an AND gate 304 is turned on to output a signal 105-3, and the error occurrence is transmitted to an address calculating unit of a CPU. Thus, the capability of error detection for undefined length instructions where the operand designator is used commonly for plural operands to be processed is improved.

9. 发明专利

JPS5817585A VIRTUAL STORAGE PROCESSOR 失效
公开(公告)号：JPS5817585A
公开(公告)日：1983-02-01
申请号：JP11299681
申请日：1981-07-21
申请人： HITACHI LTD
发明人： MIYAZAKI YOSHIHIRO , KATOU TAKESHI , IDE TOSHIYUKI
IPC分类号： G06F12/10 , G06F13/00
摘要： PURPOSE:To execute instructions of a program which does not require a page halt at a high speed, by providing a flag which is rewritable by a program in the processor in a computation system. CONSTITUTION:The status controller 17 in a execution processor has an nonnecessary flag 44 for a preliminary check on a page halt and a rehearsal flag 45 which relates to said flag in addition to negative, zero, even, overflow, and carry arithmetic indicators 39-43 for indicating arithmetic results. The arithmetic indicators 39-43 and flag 44 are part of a program status word PSW. The PSW is status information characteristic to a program which is stored in a stand-by area in a memory during stack switching, and also read therefrom to be set as a new PSW.

10. 发明专利

JPS588336A DATA TRANSFERRING METHOD 失效
公开(公告)号：JPS588336A
公开(公告)日：1983-01-18
申请号：JP10437081
申请日：1981-07-06
申请人： HITACHI LTD
发明人： YAMASHITA KENKICHI , IDE TOSHIYUKI
IPC分类号： G06F13/28
摘要： PURPOSE:To remarkably increase the transfer speed of block data, by accessing each file memory in parallel with a DMA channel and performing data transfer between the DMA channel and a main memory in time division from the result of access. CONSTITUTION:Starting is performed from a CPU 6 to DMA channels 31 and 32. In starting, the channels 31 and 32 access data, which are transferred to a main memory 1 with a transfer occupying time of a bus 4. The transfer of data is executed by the channel accessed earlier to request bus occupying right to a bus controller 5. After the transfer rate of file memories 21 and 22, the succeeding data are accessed in each file in parallel and transferred to the memory 1. When the memories 21 and 22 are magnetic bubble memories, in the transfer operation, no complete synchronizing operation is performed, but each data is surely transferred to the address of the memory 1 indicated with main memory address registers 71 and 72 by using the bus 4 in time division, allowing to remarkably reduce the entire transfer time.

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