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    • 3. 发明专利
    • DOPPLER RADAR MODULE
    • JPH0399288A
    • 1991-04-24
    • JP23756289
    • 1989-09-13
    • HITACHI LTDHITACHI TOKYO ELECTRONICS
    • OTOGURO MASATAKATANBARA HIDEOMOROSHIMA HEIJITERAKADO HAJIMEKANEKO KAZUO
    • H01P5/02G01S7/03H01P5/18
    • PURPOSE:To make an apparatus small in size and to reduce the cost thereof without turning the degree of electromagnetic coupling to be lower than usual, by disposing a strip line for electromagnetic coupling between transmission and reception antennas. CONSTITUTION:A Gunn diode H oscillates and its power is emitted from a batch antenna A for transmission. A part of the power excites the whole of a strip line B for electromagnetic coupling which overlaps with the opposite position of the antenna A, and the line B operates as a resonator. Then a strong electromagnetic field is generated and it reaches a batch antenna CA for reception which overlaps with the opposite position of the line B. Thus a reference signal as a local source from the antenna A to the antenna CA reaches the latter. Meanwhile, another signal emitted from the antenna A strikes on some object and turns to be a reflection signal of which the frequency is shifted by a Doppler effect, and it is received by the antenna CA. These reference and reflection signals flows into a Schottky diode I from the antenna CA and a difference component DELTAf of frequencies is obtained by this diode I. Then it is outputted from an IF output terminal F and the movement of the object is detected therefrom in an analyzing device or the like.
    • 4. 发明专利
    • Zener diode and its manufacture
    • ZENER二极管及其制造
    • JPS5922368A
    • 1984-02-04
    • JP13033082
    • 1982-07-28
    • Hitachi Ltd
    • MOROSHIMA HEIJIFUJII HIDEHARUISHII SEIICHITERAKADO HAJIME
    • H01L29/866H01L29/90
    • H01L29/866
    • PURPOSE:To obtain the Zener diode of noise characteristics which generate no waveform oscillation and negative resist phenomenon even in a low current region by injecting a heavy-metal diffuser or elementary particles by the irradiation of electron rays or neutron rays to a P-N junction section. CONSTITUTION:Boron is diffused annularly to an N conduction type silicon substrate 2 of approximately 400mum thickness through photolithography and diffusion technique to form a P conduction type guard ring 5 of 0.7-1.2mum depth. Boron is diffused again through photolithography and diffusion technique to form a P conduction type region 3. Gold 10 is diffused to the main surface of the silicon substrate 2, and made reach up to the P-N junction section. A surface region except the contact region of the P conduction type region 3 of the silicon substrate 2 is coated with an insulating film 6 while AuGa and Ag are laminated in the contact region in several thousand Angstrom thickness in succession through evaporation to form an electrode 7, and Ag is plated thickly onto the electrode 7 in 50mum at the same time to form an electrode 8. AuSb and Ag are also laminated on the back side of the silicon substrate 2 in serveral thousand Angstrom thickness in succession through evaporation to form an electrode 9, and a Zener diode chip 1 is formed.
    • 目的:为了获得即使在低电流区域也不产生波形振荡和负抗蚀剂现象的齐纳二极管,通过将电子射线或中子射线照射到P-N接合部分,注入重金属扩散器或基本粒子。 构成:通过光刻和扩散技术,硼通过光刻和扩散技术环状散布到约400μm厚的N +导电型硅衬底2,以形成0.7-1.2μm深度的P +导电型保护环5。 硼通过光刻和扩散技术再次扩散以形成P导电型区域3.金10扩散到硅衬底2的主表面,并到达P-N结部分。 除了硅基板2的P导电型区域3的接触区域之外的表面区域被绝缘膜6涂覆,同时通过蒸发将AuGa和Ag在数千埃厚度的接触区域中层压在一起,以形成电极7 并且Ag在同一时间以50微米厚度电镀在电极7上以形成电极8. AuSb和Ag也通过蒸发连续层叠在硅衬底2的背面上,连续地通过蒸发形成一千埃厚度,以形成电极 9,并且形成齐纳二极管芯片1。
    • 6. 发明专利
    • MANUFACTURE OF SEMICONDUCTOR DEVICE THROUGH ION IMPLANTATION
    • JPS57138132A
    • 1982-08-26
    • JP2301681
    • 1981-02-20
    • HITACHI LTD
    • OGURI KEIJIMOROSHIMA HEIJITERAKADO HAJIME
    • H01L21/265
    • PURPOSE:To manufacture the device having a desired impurity profile efficiently in a short time by implanting ions having low concentration at two or more of plural times while changing energy in a junction forming process through ion implantation. CONSTITUTION:Two conductive type determined impurities are formed to the main surface of one conductive type substrate through the ion implantation, and the device having a P-N junction is manufactured in the substrate. In the ion implanting process, ions are implanted at times such as twice when the concentration of the surface and concentration near the junction can be brought to desired values through the implantation of a condition such as 100kev, 5X10 cm . Primary implantation is executed at a condition such as 150kev, 7X10 cm , and secondary implantation is executed under the condition of 40kev, 6X10 cm . Accordingly, since the profile equal to the case when ions are implanted once can be formed, th process can be completed in a short time even when using a low current implanting device, and the efficiency of the device can be improved.
    • 7. 发明专利
    • DIODE
    • JPS56140652A
    • 1981-11-04
    • JP4357580
    • 1980-04-04
    • HITACHI LTD
    • NAITOU MASAYATERAKADO HAJIMEKUWATANI SETSUOMOROSHIMA HEIJI
    • H01L23/48H01L23/051
    • PURPOSE:To obtain a small-sized diode with a high tensile snapping strength in an axial direction and bearable to a thermal shock by a method wherein a ratio of a length (l) of a lead end placed in contact with an inner wall of a glass tube and a thickness (t) of the glass tube is defined within a prescribed range. CONSTITUTION:A dumet wire for heat sink in a thick diameter is integrated with the ends 12 of the lead 11. An Si pellet 13 is connected held at the both sides by the ends 12. The outer diameters (d) of the ends 12 are set as 0.6-0.85mm.phi from various factors. The glass tube 14 having the almost same coefficient of thermal expansion as the dumet wire is fitted and air-tightly sealed. Assuming now that the length of the end 12 is taken as (l) and the thickness as (t), the tensile snapping strength is satisfied if l/t being over approximately 1.5 and satisfactorily bearable to the thermal shock if under 2.5. Though the values are fluctuated more or less depending upon a quality of the glass and a dimension of the inside diameter, the device in high reliability can be obtained.
    • 8. 发明专利
    • METHOD FOR EVALUATING AND PRODUCING SEMICONDUCTOR CRYSTAL
    • JPS5691440A
    • 1981-07-24
    • JP16837479
    • 1979-12-26
    • HITACHI LTD
    • KUWATANI SETSUOMOROSHIMA HEIJITANBARA HIDEOFUJITA MASATOISHII SEIICHI
    • H01L21/66G01R31/28
    • PURPOSE:To evaluate a crystal accurately from its impurity distribution by providing the measuring terminals of P-N junctions or Schottky barriers on the measured surface of a semiconductor crystal to obtain capacitance-voltage characteristics and computing the depth of a depletion layer and the concentration of immurities from the results. CONSTITUTION:When evaluting a crystal for a varicap diode, an N type Si substrate with an N type epitaxial layer 1 is prepared and an oxide film 3 with openings 4 is formed over the epitaxial layer 1. Four of such openings positioning at the apexes of a square are grouped into one set and five sets are provided in the center and the peripheral parts of the quarters of the wafer. P type regions 5 are provided in the epitaxial layer through the openings and C-V characteristics are measured with a measuring electrode. The concentration of impurities and the depth of a depletion layer are computed from the characteristics and impurity distribution is determined. And from the results of the five positions, the wafer is judged to be good or bad. By so doing, the accuracy of evaluating crystals is improved and their available percentage can be increased. Schottky barrier diodes can also be evaluated in the same way.
    • 9. 发明专利
    • DIODE ARRAY
    • JPS5685872A
    • 1981-07-13
    • JP16153279
    • 1979-12-14
    • HITACHI LTD
    • MOROSHIMA HEIJITERAKADO HAJIMENAITOU MASAYA
    • H01L25/11H01L29/861H01L29/91
    • PURPOSE:To obtain a diode array having desired number of elements by arranging a plurality of diodes having equal characteristics at an equal interval, fixing the ends of the lead wires projected from these diodes with cladding tape, conducting the common leads of the respective diodes with a shortcircuit bar using conductors and sealing them. CONSTITUTION:A plurality of diodes 1 having equal characteristics are arranged at an equal interval in parallel with each other while directing the polarity display formed on a sealer 2 in the same direction, and then ends of lead wires 3 projected at both ends thereof are fixed with cladding tape formed of tapes 4 and 5. Subsequently, the common lead wires of the respective diodes are conducted with shortcircuit bars 6 using conductors 7, and a sealer 2 is integrated with an auxiliary sealer 8 using resin. Thus, desired diode array 9 is formed, and when using it, the tapers 4 and 5 are pulled and exfoliated. That is, the array is simplified into a sole unit, thereby shortening the mounting time period of the array in use.