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1. 发明专利

JPH10336004A SEMICONDUCTOR INTEGRATED CIRCUIT AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH10336004A
公开(公告)日：1998-12-18
申请号：JP14645497
申请日：1997-06-04
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： TANIMOTO MASAAKI , TAKEDA TAKAHIDE , YAMAGISHI KAZUSHIGE , KIKUCHI AKIRA
IPC分类号： H03K19/0175
摘要： PROBLEM TO BE SOLVED: To enable the amplitude of the interface signal with the outside of a semiconductor integrated circuit using a single power source to select both a voltage which is nearly equal to a power supply voltage and a lower voltage. SOLUTION: A logic circuit 16 selects either a current route Vdd, MP27, MP2, and 13 through which a high-level output voltage which is nearly equal to an external power supply voltage Vdd is supplied to an external signal terminal PDi or another current route Vdd, MP6, MN2, and 13 through which a high-level output voltage which is lower than the external power supply voltage Vdd is supplied to the signal terminal PDi in accordance with the state of a mode signal MODE. The on-resistance or mutual conductances of the current routes are made different from each other so that the output voltage levels of the routes may become different from each other without making any through current to flow.

2. 发明专利

JP2002328832A MEMORY CONTROLLER 失效
公开(公告)号：JP2002328832A
公开(公告)日：2002-11-15
申请号：JP2001135722
申请日：2001-05-07
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： NARITA MASAHISA , NAKATSUKA YASUHIRO , MORITA YUICHIRO , YAMAGISHI KAZUSHIGE , OKADA YUTAKA
IPC分类号： G06F11/34 , G06F12/00 , G09G5/00 , G09G5/393
摘要： PROBLEM TO BE SOLVED: To enable a display device to obtain required access frequency in fixed period and to simultaneously enable a CPU and a plotting device to make best use of accessibility to a memory owned by a microcomputer system having the CPU, the plotting device and the display device in the system. SOLUTION: The memory controller is provided with a control/mode register in which write is possible from the CPU, an access report detecting circuit, a priority level-judging circuit, a timer and a status register capable of read from the CPU. It periodically monitors accesses to the respective devices, stores them in the status register accessible from the CPU, compares a value of the status register with a restriction register set by software and can change priority level of the next prescribed period.

3. 发明专利

JP2002132578A DATA PROCESSING SYSTEM 审中-公开
公开(公告)号：JP2002132578A
公开(公告)日：2002-05-10
申请号：JP2001243069
申请日：2001-08-10
申请人： HITACHI LTD
发明人： SATO JUN , YAMAGISHI KAZUSHIGE , NAKAJIMA KEISUKE , KATSURA AKIHIRO , MIYAMOTO TAKASHI , OMURA KENICHIRO , WATABE MITSURU
IPC分类号： G11C11/407 , G06F12/00 , G06F12/02
摘要： PROBLEM TO BE SOLVED: To provide a data processing system using a memory such as a synchronous DRAM which has data input-output capability, based on clock synchronization. SOLUTION: The system has a CPU 15, a memory 22 that performs data input-output with clock synchronization, and a memory control device 11. The memory control device is provided with a CPU interface 19 connected to the CPU, a memory interface 14 that is connected to the memory and control parts 12, 13. The CPU interface performs delivery of data between the CPU by receiving a predetermined control signal from the CPU. The control part executes write/read in the memory depending on the control signal from the CPU through the memory interface part. The memory interface has a plurality of terminals for supplying the control signal to the memory to deliver the data, and data exchange is performed in synchronism with the clock signal supplied to the memory through the plurality of terminals.

4. 发明专利

JPH11296154A DEVICE AND METHOD FOR GRAPHIC PROCESSING 失效
公开(公告)号：JPH11296154A
公开(公告)日：1999-10-29
申请号：JP10434298
申请日：1998-04-15
申请人： HITACHI LTD
发明人： SHIMOMURA TETSUYA , MATSUO SHIGERU , KOGA KAZUYOSHI , KATSURA AKIHIRO , NAKATSUKA YASUHIRO , YAMAGISHI KAZUSHIGE
IPC分类号： G06F13/18 , G06F12/00 , G06F12/02 , G06T1/60 , G09G5/00
摘要： PROBLEM TO BE SOLVED: To conduct an arbitration so that plural circuits, which are required to complete their processes within a normal time, make necessary and sufficient accesses to a memory. SOLUTION: A bus controlling circuit 200 compares the degree of urgency for the access to a memory 700 of each circuit, dynamically determines the priority of an internal bus 110 using internal state signals 311, 321, 331 and 341 outputted from a CPU I/F circuit 310, a plotting circuit 320, a video input circuit 330 and a display circuit 340 and conducts bus arbitration of the bus 110 using the priority. Thus, even though there exist plural circuits, which must complete their processes within a normal time, a necessary and sufficient memory access is conducted to complete the respective processes within the normal time.

5. 发明专利

JPH0962862A PLOTTING METHOD AND GRAPHIC DEVICE 失效
公开(公告)号：JPH0962862A
公开(公告)日：1997-03-07
申请号：JP22022595
申请日：1995-08-29
申请人： HITACHI LTD
发明人： NAKAJIMA KEISUKE , KATSURA AKIHIRO , NAKATSUKA YASUHIRO , MATSUO SHIGERU , NARITA MASAHISA , SATO JUN , SONE TAKASHI , YAMAGISHI KAZUSHIGE
IPC分类号： G06T1/20 , G06T1/00 , G06T15/04 , G06T15/00
摘要： PROBLEM TO BE SOLVED: To provide a graphic device which executes a high speed texture mapping processing while high picture quality is kept. SOLUTION: A graphic processor 10 is provided with a scanning method selection part 102. Either a mode for horizontally scanning data of a source picture area by one dot or a mode for horizontally scanning data of a plotting picture area by one dot is selected by designation from a command and the characteristic (number of angles and flat rate calculation result) of a graphic.

6. 发明专利

JP2002342159A MEMORY CONTROLLER 失效
公开(公告)号：JP2002342159A
公开(公告)日：2002-11-29
申请号：JP2001151223
申请日：2001-05-21
申请人： HITACHI LTD
发明人： MORITA YUICHIRO , JO MANABU , NAKATSUKA YASUHIRO , SHIMOMURA TETSUYA , OKADA YUTAKA , YAMAGISHI KAZUSHIGE
IPC分类号： G06F12/06 , G06F12/00 , G06F12/02 , G06F13/16 , G11C11/401 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To efficiently make access to a dynamic random access memory. SOLUTION: When a device outputs an access request to a memory controller 1, the memory controller 1 activates a page designated with a row address ra0 in a band b0 in a memory cycle a0 on the basis of the access request, subsequently performs preceding precharge to a bank 1 to be the next access object before performing read access to the page of the bank b0. The memory controller 1 immediately performs activation of a bank b1 without performing precharge when page mishit occurs in accessing the bank b1 from the bank 0 because of drawing processing after read access of the bank b0.

7. 发明专利

JP2002073526A MEMORY ACCESS SYSTEM 失效
公开(公告)号：JP2002073526A
公开(公告)日：2002-03-12
申请号：JP2000254986
申请日：2000-08-25
申请人： HITACHI LTD
发明人： NAKATSUKA YASUHIRO , SHIMOMURA TETSUYA , JO MANABU , MORITA YUICHIRO , HOTTA TAKASHI , YAMAGISHI KAZUSHIGE , OKADA YUTAKA
IPC分类号： G06F13/16 , G06F3/153 , G06F12/00 , G06F12/04 , G09G5/39
摘要： PROBLEM TO BE SOLVED: To provide a memory access system suitable for suppressing increase in latency and suppressing lowering of system performance even in a memory integrating configuration. SOLUTION: The basic part of a multimedia data processor is composed of a CPU 1100, an image display device 2100, an integrated memory 1200, a system bus 1920 and input/output devices 1300, 1400 and 1500 connected thereto. In this case, the CPU is formed into LSI packaged on single silicon provided with an instruction processing part 1110 and a display control part 1140. The integrated memory stores a main storage area 1210 and a display area 1220. Then, an integrated memory port 1910 between this LSI and the integrated memory is provided separately and independently of a system bus between this LSI and the input/output device. The integrated memory port can be driven at a speed higher than in the system bus.

8. 发明专利

JP2000181431A GRAPHIC PROCESSOR 失效
公开(公告)号：JP2000181431A
公开(公告)日：2000-06-30
申请号：JP35227198
申请日：1998-12-11
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： NAKATSUKA YASUHIRO , SONE TAKASHI , YAMAGISHI KAZUSHIGE , NARITA MASAHISA
IPC分类号： H04N5/262 , G09G5/00 , H04N5/45
摘要： PROBLEM TO BE SOLVED: To obtain an apparatus capable of executing deformed plotting using input videos as original data and executing high-quality display by constituting the apparatus in such a manner that the video data stored by a video input means can be referenced from a graphic generating means as well in addition to display. SOLUTION: Memories to be exclusively used which are heretofore discretely arranged are integrated as an architecture having a single address space which is common in respective mechanisms for videos, graphics and display and allows the utilization of free addresses. The apparatus is so constituted that graphic processing portions can reference the video input data region at this time. The apparatus accesses an external memory, such as a main memory 1200, via an instruction processing section 1110, a video input section 1120, a pixel generating section 1130, a display control section 1140, an I/O section 1160 and a bus control section 1150. These accesses are generated by a storage request of the store address memory type pixel generation command from the instruction processing section 1110, a storage request for video data, a reading out request for displaying the stored graphic and video data, etc.

9. 发明专利

JP2000172553A DATA PROCESSOR 失效
公开(公告)号：JP2000172553A
公开(公告)日：2000-06-23
申请号：JP35227098
申请日：1998-12-11
申请人： HITACHI LTD
发明人： JO MANABU , SHIMOMURA TETSUYA , MATSUO SHIGERU , NAKATSUKA YASUHIRO , YAMAGISHI KAZUSHIGE
IPC分类号： G09G5/00 , G06F12/00
摘要： PROBLEM TO BE SOLVED: To efficiently use a bus by outputting an address for reading the next data from a memory to the memory while a memory controller reads data from the memory. SOLUTION: Plural different busy signals are outputted depending on the kind of access to be performed next by a processor and a bus arbitration controller outputs bus use permission signals to the processor at an optimum timing corresponding to the signals and the kind of the access scheduled to be performed next. Then, in the case of accessing the memory, at the point of time of ending the output of the address required for the access performed at present to an address bus, in the case that a data bus does not collide, the address required for the next access is outputted to the address bus. In the device, a bus arbitration circuit 600 performs the bus arbitration of the internal bus of the memory controller 500. A CPU interface circuit 700 performs control for making a CPU 100 access register kinds such as a memory mode register 1200 and the memory 200.

10. 发明专利

JP2000020044A IMAGE PROCESSOR 失效
公开(公告)号：JP2000020044A
公开(公告)日：2000-01-21
申请号：JP18855798
申请日：1998-07-03
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAKEBE ISAO , MATSUO SHIGERU , KOGA KAZUYOSHI , SHIN YOSHITAKA , NAKATSUKA YASUHIRO , YAMAGISHI KAZUSHIGE , KANAMARU KATSUO
IPC分类号： G09G5/06 , G06T1/00 , G06T11/60
摘要： PROBLEM TO BE SOLVED: To prevent deterioration in picture quality even in the case of displaying with various application programs by mapping from the color data of (a) bits to a color set in a color palette and gradation-reducing to the color data of (m) bits equal to or smaller than (a) bits. SOLUTION: In the case of an index color mode, a display of an image reads out successively the index pixel data stored in a frame buffer 141, and converts the index pixel data to the RGB data by the color palette 132 to send them to a DAC 133. A CPU 11 converts the image data to the color data of (a) bits, and selects a pixel conversion filter 112 long in processing time in the case of displaying a still image, and selects the pixel conversion filter 112 short in processing time in the case of displaying an animation. Then, the CPU 11 maps from the color data of (a) bits to the color set in the color palette 132, and gradation-reduces to the color data of (m) bits equal to or smaller than (a) bits.

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