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1. 发明专利

JPH04318612A BUS CONTROL SYSTEM 失效
公开(公告)号：JPH04318612A
公开(公告)日：1992-11-10
申请号：JP8655191
申请日：1991-04-18
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SHIBATA NAOAKI , ITO KAZUKO , ONISHI KATSUYOSHI , GOTOU KAZUMICHI , SUZUKI NAOKI
IPC分类号： G06F3/00 , G06F13/40
摘要： PURPOSE:To miniaturize the device and to reduce the assembling man-hour by eliminating the pull-up/pull-down resistance of the bus signal as much as possible and to prevent the generation of the signal noise by defining the bus signal line as an irreducible minimum electrical amplitude by not performing the pull-up for the bus signal line. CONSTITUTION:The signal line of a bus 10 is driven to a high or low level by the bus signal line drive circuit of a bus control device 13. The bus control device 13 recognizes which device of each device of 11, 12, 14 and 15 connected with the bus 10 within the information processing device uses the bus 10 or does not use. As a result, the device 13 recognizes the presence or absence of the device which drives the bus 10 at present. While every device connected with the bus does not drive the bus signal, or in the case that the bus signal line becomes high impedance state if the period when the bus signal is not driven continues, the bus control device 13 drives the bus signal line.

2. 发明专利

JPH04321993A STORAGE CONTROL DEVICE 失效
公开(公告)号：JPH04321993A
公开(公告)日：1992-11-11
申请号：JP9198491
申请日：1991-04-23
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： GOTOU KAZUMICHI , SHIBATA NAOAKI , UCHIDA MITSUTOSHI , SUZUKI NAOKI
IPC分类号： G06F5/10 , G06F5/06 , G11C7/00 , H04J3/06
摘要： PURPOSE:To write individual data in the address of a second storage circuit by successively storing in a first storage circuit the write address and the write data of the second circuit and then reading them out of the first circuit. CONSTITUTION:When a write request signal 113 to the second storage circuit 102 is inputted in a input control circuit 114, the write address 103 of the circuit 102 is selected by a selector 106, a write signal 119 is generated by a write circuit 118, and the address 103 is written in the O-order of the first storage circuit 101. Then, the write data 105 is selected by the selector 106, and the data 105 is written in the 1st word of the circuit 101. Then, by a control signal 122 from an output control circuit 121, the write address 108a is read from the O-order word of the circuit 101 and written in the address register 109 of the circuit 102. Successively, the write data 108b is read from the 1st word and written in the data register 111 of the circuit 102.

3. 发明专利

JPH10257059A ATM CONTROLLER, ATM COMMUNICATION CONTROL EQUIPMENT AND ITS OUTPUT CONTROL METHOD 失效
公开(公告)号：JPH10257059A
公开(公告)日：1998-09-25
申请号：JP5190597
申请日：1997-03-06
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK
发明人： YOKOYAMA TATSUYA , WATANABE YOSHIKI , GOTOU KAZUMICHI , MIZUTANI MIKA , HATA EIZO
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide an ATM communication control equipment and an ATM controller with more effective traffic shaving functions. SOLUTION: A mediation processing part 104 is provided with a table in which a storage area to store a cell transmission request by every logic connection is provided and a pointer to indicate the storage area of the table corresponding to the logic connection to be outputted next and to be transferred according to an order of output. The cell transmission request is stored in the storage area of the table corresponding to the logic connection of the cell transmission request when the cell transmission request is instructed by each timer with respect to the mediation processing part 104. In addition, cell transmission requests are successively outputted by referring to the storage area of the table indicated by the pointer. After each cell is outputted, the cell transmission request to be outputted is successively changed by successively adding one to the pointer.

4. 发明专利

JPH0476656A MULTIPLE DISPLAY SYSTEM DEVICE 失效
公开(公告)号：JPH0476656A
公开(公告)日：1992-03-11
申请号：JP18678090
申请日：1990-07-12
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： ISHITOBI MUTSUHIKO , YAMADA AKIRA , GOTOU KAZUMICHI , SADAMITSU HITOSHI , UCHIDA MITSUTOSHI , MITANI KATSUYA , KAWAI TAKAHIRO , SAKUYAMA HIDEO
IPC分类号： G06F3/153 , G06F1/00 , G06F15/00
摘要： PURPOSE:To control plural input/output devices independently of one another by incorporating plural screen display type input output device sets each consisting of a pair of a display unit and a keyboard in the system device. CONSTITUTION:Sets of the display units 10 which have power lamps 13 and power switches 14, keyboards 11, and mouses 12 are connected to the connector of the I/O board of one display keyboard control part. The I/O board of the display control part is connected to the base substrate of the system device by a plug-in system and the sets of the display units 10, keyboards 11, and mouses 12 are connected to the display keyboard control parts (5, 6, and 7) to constitute the system of the multiple display system device equipped with the plural display units, keyboards, and mouses.

5. 发明专利

JPH0474249A BUS CONTROL SYSTEM 失效
公开(公告)号：JPH0474249A
公开(公告)日：1992-03-09
申请号：JP18847790
申请日：1990-07-16
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI COMPUTER ELECTRONIC
发明人： SHIBATA NAOAKI , GOTOU KAZUMICHI , FUJIMURA ATSUSHI , UCHIDA MITSUTOSHI
IPC分类号： G06F13/36
摘要： PURPOSE:To attain the transfer of data at a high speed by transferring data with time division control by means of plural 1st signal lines on which the addresses or data are put, plural 2nd signal lines on which the attribute information or data are put, and a control signal line on which the control information is put. CONSTITUTION:An information processor 11 starts the use of a bus with a bus use grant BG signal of a bus controller 13 and sends the read addresses of a memory 12 to the address signal lines AD28-AD0 and the data transfer sizes and the data transfer directions to the bus transfer control lines CD31-CD29, At the same time, the processor 11 transmits a valid signal to an address valid signal line AV. The memory 12 analyzes the signals of the lines AD28 and CD31, sends the data read out of the memory 12 itself to the lines CD31 and AD28 and a valid signal to a data valid signal line DV respective ly. The processor 11 recognizes the transmission of data with the valid signal and fetches the data sent to both lines CD31 and AD28 to complete a series of reading cycles.

6. 发明专利

JPH04136897A CURSOR COORDINATE SETTING CONTROLLER 失效
公开(公告)号：JPH04136897A
公开(公告)日：1992-05-11
申请号：JP25691290
申请日：1990-09-28
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： GOTOU KAZUMICHI , UCHIDA MITSUTOSHI , MURAKAMI MASAYUKI , SUZUKI NAOKI
IPC分类号： G06F3/14 , G06F3/048 , G09G5/08
摘要： PURPOSE:To secure a specific display response time and to securely make a response and a display by storing cursor coordinate positions in 1st X and Y coordinate registers and outputting them through 2nd X and Y coordinate registers in synchronism with specific time intervals. CONSTITUTION:The X and Y coordinates outputted by a central processing unit 1 are set in the 1st X and Y coordinate registers 2 with the control signal (a) outputted by the controller 5 for the 1st X and Y coordinate registers and outputted to the 2nd X and Y coordinate registers 3. The X and Y coordinates outputted by the registers 2 are set in the registers 3 with the control signal (b) outputted by the controller 6 for the 2nd X and Y coordinate registers and also outputted to a cursor generation device 4. At this time, the signal outputted by the device 6 operate in unit of time wherein an average operator can view the cursor and respond. This constitution makes a display on a display device, etc., which is fast in display response speed respond to human view.

7. 发明专利

JPS59218566A Memory access circuit 失效
标题翻译：存储器访问电路
公开(公告)号：JPS59218566A
公开(公告)日：1984-12-08
申请号：JP9237183
申请日：1983-05-27
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： AMANO YOSHIKAZU , GOTOU KAZUMICHI
IPC分类号： G06F12/04 , G06F13/00 , G11C7/00
CPC分类号： G06F13/00
摘要： PURPOSE:To execute rewriting of data of only optional bits, and to shorten a processing time by dividing a write operation of a memory into two, and writing new data for every bit, or selecting the preservation of contents of the memory. CONSTITUTION:Respective switches SW1-8 of a bit write controlling circuit 13 are connected to an A side or a B side in each bit unit. As a result, it becomes possible that MPU data whose writing is executed at 1 byte unit is written in each bit unit, or the previous data written in an RAM is preserved. A bit mask controlling latch circuit 12 controls whether each switch SW1-SW8 of the bit write controlling circuit 13 is connected to the A side or the B side. Also, the bit mask controlling latch circuit 12 determines whether the data is rewritten for every bit, or the data on the RAM4 is preserved.
摘要翻译：目的：执行只有可选位的数据重写，并通过将存储器的写入操作除以2来缩短处理时间，并为每个位写入新数据，或选择保存存储器的内容。构成：位写入控制电路13的各开关SW1-8在每个位单元中连接到A侧或B侧。结果，可以将以1字节为单位执行写入的MPU数据写入每个位单元，或者保留写入RAM中的先前数据。位掩码控制锁存电路12控制位写入控制电路13的每个开关SW1-SW8是连接到A侧还是B侧。此外，位掩码控制锁存电路12确定是否为每一位重写数据，或者保留RAM4上的数据。

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