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1. 发明专利

JPH0645594A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0645594A
公开(公告)日：1994-02-18
申请号：JP5872592
申请日：1992-03-17
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI INSTRUMENTS ENG
发明人： UCHIYAMA HIROYUKI , YONEOKA TAKU , MIYAZAWA HIROYUKI , WATABE KOZO , OGISHIMA JUNJI , KANEKO YOSHIYUKI , ASAYAMA MASAICHIRO , NAGAO MAKI , SUWAUCHI NAOKATSU
IPC分类号： H01L29/78 , H01L29/784
摘要： PURPOSE:To improve the characteristics of a semiconductor integrated circuit device having a MISFET and to improve the yield of the device. CONSTITUTION:Oxidation-resistant films 4 and 6 are respectively provided on the upper part and sidewalls of a gate electrode of a MISFET Q and oxide films 5 and 8 are respectively provided on the upper part and sidewalls of the gate electrode 3 via these films 4 and 6. Accordingly, as the path of oxygen to intrude through the films 5 and 8 on the upper part and sidewalls of the gate electrode 3 is blocked by the films 4 and 6, oxidation of an oxidizable conductive film constituting the electrode 3 is less, and crystal defects in the main surface part of a semiconductor substrate 1, which is caused by the volume expansion of the substrate, can be reduced.

2. 发明专利

JPH02246150A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, ITS FORMATION AND APPARATUS FOR PRODUCING IT 失效
公开(公告)号：JPH02246150A
公开(公告)日：1990-10-01
申请号：JP6584889
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MURATA JUN , TADAKI YOSHITAKA , KANEKO HIROKO , SEKIGUCHI TOSHIHIRO , UCHIYAMA HIROYUKI , NAKAMURA TAKASHI , MAEDA TOSHIO , KASAHARA OSAMU , ENAMI HIROMITSU , OGISHIMA JUNJI , NAGAO MAKI , FUNAHASHI TOMOMASA , KIGUCHI YASUO , KOJIMA MASAYUKI , KOIKE ATSUYOSHI , MIYAZAWA HIROYUKI , SADAOKA MASATO , KADOTA KAZUYA , CHIGAWARA TADASHI , NOJIRI KAZUO , KOBAYASHI YUTAKA
IPC分类号： H01L27/04 , H01L21/027 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To increase a charge storage amount of a capacity element, for information storage use, of a stacked structure and to enhance an alpha-ray soft-error breakdown strength and an integration density of a DRAM by a method wherein a correction pattern which increases a surface area of a lower-layer electrode layer is formed on the lower-layer electrode structure of the capacity element, for information storage use, of the stacked structure of a memory cell of the DRAM. CONSTITUTION:A capacity element C, for information storage use, of a memory cell M is constituted in such a way that a lower-layer electrode layer 33, a dielectric film 34 and an upper-layer electrode layer 35 are laminated one after another. The capacity element C for information storage use is constituted in a so-called stacked structure. In the lower-layer electrode layer 33, a correction pattern 33A protruding in a plane direction from a region formed in a plane square shape is formed on the connection side of an n-type semiconductor region 28 and a complementary data line 50. A size of an etching mask used to process the lower-layer electrode layer 33 is reduced by reflected light; accordingly, a size of the lower-layer electrode layer 33 is made smaller than a preset value. Then, the correction pattern 33A is constituted in such a way that the size of the lower-layer electrode layer 33 is made large in anticipation of a reduced portion of the size.

3. 发明专利

JPH08241970A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241970A
公开(公告)日：1996-09-17
申请号：JP6474596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MURATA JUN , TADAKI YOSHITAKA , KANEKO HIROKO , SEKIGUCHI TOSHIHIRO , UCHIYAMA HIROYUKI , NAKAMURA TAKASHI , MAEDA TOSHIO , KASAHARA OSAMU , ENAMI HIROMITSU , OGISHIMA JUNJI , NAGAO MAKI , FUNAHASHI TOMOMASA , KIGUCHI YASUO , KOJIMA MASAYUKI , KOIKE ATSUYOSHI , MIYAZAWA HIROYUKI , SADAOKA MASATO , KADOTA KAZUYA , CHIKAWAHARA TADASHI , NOJIRI KAZUO , KOBAYASHI YUTAKA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which reduces a disconnection defect or the like in the stepped part of the interconnection of a word line for a shunt by a method wherein a memory cell in a first region and a memory cell in a second region are connected by a common gate electrode in such a way that respective word lines are connected across both regions and a conductive layer which is the same layer as the electrode of a capacitance element is formed across both regions. CONSTITUTION: MISFET's Qs's for memory selection of a plurality of memory cells M are constituted on the main face part of p-well regions 22, and they are constituted mainly of the p-well regions 22, of gate insulating films 25, of gate electrodes 26 and of one pair of n-type semiconductor regions 28 as a source region and a drain region. The gate electrodes 26 and word lines 26 are formed respectively of the same conductive layer, and the word lines connect the respective gate electrodes 26 of the MISFET's for Qs's for memory selection of the plurality of memory cells M arranged in the row direction. In addition, n-type semiconductor regions 28 on the connection side of capacitance elements C, for information storage, of the MISFET's Qs's for memory selection are constituted integrally with n semiconductor regions 33A.

4. 发明专利

JPH02246149A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR REMEDYING DEFECT THEREOF 失效
公开(公告)号：JPH02246149A
公开(公告)日：1990-10-01
申请号：JP6583989
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： SAKUTA TOSHIYUKI , ISHIHARA MASAMICHI , MIYAZAWA KAZUYUKI , HIROKI MASANORI , IWAI HIDETOSHI , NAKAMURA TAKASHI , TAKAHASHI YASUSHI , MAEDA TOSHIO , MATSUURA NOBUMI , HORI RYOICHI , SASAKI TOSHIO , SAKAI OSAMU , UCHIYAMA HIROYUKI
IPC分类号： G11C29/00 , G11C11/401 , G11C11/406 , G11C29/04 , H01L21/82 , H01L27/10
摘要： PURPOSE:To simplify and rationalize a layout by a method wherein a circuit having a RAM function is formed as a macrocell and a plurality of macrocells constitute a semiconductor storage circuit of a large storage capacity. CONSTITUTION:In this RAM, a plurality of memory blocks which has been formed as macrocells are arranged in a matrix manner. Sixteen memory blocks of about 4 Mbits each are arranged in four rows and four columns and have a large storage capacity of about 64 Mbits as a whole. One memory block constituted as the macrocell is provided with the following: a row-based address decoder which receives an address signal supplied through a timing/address generation circuit which have been made common; an address selection circuit composed of a word-line drive circuit, a column-based address decoder, a column selection-line drive circuit or the like; a timing generation circuit which generates a time-series timing pulse when an internal operation is required according to a memory array and an operating mode; a timing generation circuit for a selected memory cell; an input/output circuit which executes a write/readout operation of a data for the selected memory cell.

5. 发明专利

JPH0548028A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0548028A
公开(公告)日：1993-02-26
申请号：JP20164691
申请日：1991-08-12
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI INSTRUMENTS ENG
发明人： UCHIYAMA HIROYUKI , OGISHIMA JUNJI , MIYAZAWA HIROYUKI , WATABE KOZO , NAGAO MAKI , ASAYAMA MASAICHIRO , YONEOKA TAKU , KANEKO YOSHIYUKI , SUWAUCHI NAOKATSU
IPC分类号： H01L27/10 , H01L27/12
摘要： PURPOSE:To enable electrical reliability to be improved in a semiconductor integrated circuit device with a volatile memory circuit. CONSTITUTION:In a semiconductor integrated-circuit device with a MISFETQt constituting a volatile memory circuit, an insulation film 2 is provided on a main surface of a semiconductor substrate 1 excluding one portion, a single- crystal silicon film 5 is provided on this insulation film 2 and on one portion of the main surface of the semiconductor substrate 1, a channel region of the MISFETQt is provided at the main-surface portion of the single-crystal silicon film 5 on one portion of the main surface of this semiconductor substrate 1, and then a source region and a drain region 9 are provided on a main-surface portion of the single-crystal silicon film 5 on the insulation film 2, thus enabling a substrate bias to be supplied. A p-n junction area which is constituted by the source region and the drain region 9 as well as the semiconductor substrate 1 is reduced.

6. 发明专利

JPH053301A SEMICONDUCTOR MEMORY CIRCUIT AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH053301A
公开(公告)日：1993-01-08
申请号：JP31042591
申请日：1991-11-26
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI INSTRUMENTS ENG
发明人： SUWAUCHI NAOKATSU , MIYAZAWA HIROYUKI , OGISHIMA JUNJI , NAGAO MAKI , ASAYAMA MASAICHIRO , UCHIYAMA HIROYUKI , KANEKO YOSHIYUKI , WATANABE KOZO , ENDO KAZUYA , SOEDA KOKI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To ensure the precision in wiring work for a memory cell array and a peripheral circuit regions by providing the third insulating film between the first and second insulating films on the second MISFET gate electrode in the peripheral circuit region. CONSTITUTION:An interlayer insulating film 31 is provided to increase the capacitance of a capacitive element for storing information in a memory array region. A connection holes 40A is drilled in interlayer insulating films 31, 39, 40 with the interlayer insulating film 31 left in a peripheral circuit region. Thus, the precision in working the connection hole 40A is improved. A wiring 50, the first metal wiring layer, is made as a pattern with the interlayer insulating film 31 left in the peripheral circuit region. Therefore, the difference between the distance from the rear face of semiconductor substrate 20 to the first metal wiring layer in the memory cell array region and that in the peripheral circuit region can be reduced to 1.5mum or less. This enables precise working of the wiring 50.

7. 发明专利

JPH08241971A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241971A
公开(公告)日：1996-09-17
申请号：JP6474696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MURATA JUN , TADAKI YOSHITAKA , KANEKO HIROKO , SEKIGUCHI TOSHIHIRO , UCHIYAMA HIROYUKI , NAKAMURA TAKASHI , MAEDA TOSHIO , KASAHARA OSAMU , ENAMI HIROMITSU , OGISHIMA JUNJI , NAGAO MAKI , FUNAHASHI TOMOMASA , KIGUCHI YASUO , KOJIMA MASAYUKI , KOIKE ATSUYOSHI , MIYAZAWA HIROYUKI , SADAOKA MASATO , KADOTA KAZUYA , CHIKAWAHARA TADASHI , NOJIRI KAZUO , KOBAYASHI YUTAKA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which reduces a short channel effect and which enhances a DRAM integration degree further by a method wherein protrusion parts are formed in parts to be used as gate electrodes of word lines used as the gate electrodes of MISFET's and the width and the interval of the respective gate electrodes are formed to be larger than the width and the interval of word lines on a field insulating film. CONSTITUTION: Word lines 26 connect respective gate electrodes 26 of MISFET's Qs's for selection of a plurality of memory cells M. In the word lines 26, protrusion parts 26A are formed on the side of other adjacent word lines 26 along the shape of the memory cells. The protrusion parts 26A are used substantially as gate electrodes of the MISFET's Qs's for selection of the memory cells, and a gate length size is made long as compared with the interconnection size of the word lines 26. In addition, an isolation size on an insulating film (a field insulating film) 23 for element isolation can be ensured sufficiently as compared with an isolation size A between the word lines 26 when the interconnection size of the word lines 26 is prescribed simply by the gate length size of the MISFET's Qs's for selection of the memory cells.

8. 发明专利

JP2014013851A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014013851A
公开(公告)日：2014-01-23
申请号：JP2012151027
申请日：2012-07-05
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI , WAKANA HIRONORI
IPC分类号： H01L29/786 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a technology of enabling improvement of performance of a semiconductor device.SOLUTION: A thin film transistor 10 includes a wire member 12 supported on a support substrate 11. The wire member 12 has as a core, a conductor wire 20 which functions as a gate line, and a surface of the conductor wire 20 is sequentially covered with a gate insulation film 21 and a channel layer 22. The wire member 12 is supported in a sandwiched manner by source/drain electrodes 13, 14 formed on the support substrate 11. The source/drain electrodes 13, 14 are electrically connected with the channel layer 22 at positions away from each other along a circumferential direction of a cross section of the wire member 12.
摘要翻译：要解决的问题：提供能够提高半导体器件的性能的技术。解决方案：薄膜晶体管10包括支撑在支撑基板11上的线构件12.线构件12具有作为芯的导线 20，其用作栅极线，并且导体线20的表面依次被栅极绝缘膜21和沟道层22覆盖。线构件12以形成的源极/漏极13,14夹持的方式被支撑源极/漏极13,14沿着线构件12的横截面的圆周方向彼此远离的位置与沟道层22电连接。

9. 发明专利

JP2013125782A Oxide semiconductor device 审中-公开
标题翻译：氧化物半导体器件
公开(公告)号：JP2013125782A
公开(公告)日：2013-06-24
申请号：JP2011272337
申请日：2011-12-13
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI , KAWAMURA TETSUSHI , WAKANA HIRONORI , OZAKI HIROAKI , YAMAZOE TAKANORI
IPC分类号： H01L29/786 , G02F1/1368
摘要： PROBLEM TO BE SOLVED: To provide an oxide semiconductor device having good characteristics and high reliability even when a flexible substrate is used.SOLUTION: An oxide semiconductor device has: a gate electrode 2; a gate insulating layer 3 provided on the gate electrode 2; a channel part provided on the gate electrode 2 via the gate insulating layer 3; and source-drain electrodes 6 electrically connected with the channel part. The channel part includes an oxide semiconductor layer 5 and a conductive layer 4. At least one of the source-drain electrodes 6 is connected to the conductive layer 4 via the oxide semiconductor layer 5.
摘要翻译：要解决的问题：即使使用柔性基板，也提供具有良好特性和高可靠性的氧化物半导体器件。解决方案：氧化物半导体器件具有：栅电极2; 设置在栅极电极2上的栅极绝缘层3; 经由栅极绝缘层3设置在栅极电极2上的沟道部分; 以及与沟道部电连接的源极 - 漏极电极6。沟道部分包括氧化物半导体层5和导电层4.至少一个源 - 漏电极6经由氧化物半导体层5连接到导电层4.版权所有（C）2013，JPO和INPIT

10. 发明专利

JP2010192560A Method of manufacturing field effect transistor having oxide semiconductor 有权
标题翻译：制造具有氧化物半导体的场效应晶体管的方法
公开(公告)号：JP2010192560A
公开(公告)日：2010-09-02
申请号：JP2009033577
申请日：2009-02-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： WAKANA HIRONORI , UCHIYAMA HIROYUKI , KAWAMURA TETSUSHI , SAITO SHINICHI
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L21/02631 , H01L21/02554 , H01L21/02565 , H01L29/7869
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a field effect transistor which has high alignment accuracy between a gate electrode and source and drain electrodes and achieves a transparent device inexpensively. SOLUTION: Since a patterned light blocking film 102 is formed on the rear side of a substrate 101 and used as a photomask for forming a pattern of the gate electrode 103 and a pattern of the source and drain electrodes 108 on the front side of the substrate, the number of photomasks is reduced, and self-alignment between the gate electrode and the source and drain electrodes is carried out, thereby improving the alignment accuracy of these electrodes. Thereby, the method of manufacturing the high-accuracy inexpensive field effect transistor can be provided. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种在栅电极和源漏电极之间具有高对准精度的场效应晶体管的制造方法，并且廉价地实现透明器件。解决方案：由于在基板101的背面形成有图案遮光膜102，并且用作用于形成栅电极103的图案的光掩模和前侧的源极和漏电极108的图案，光掩模的数量减少，并且进行栅电极与源漏电极之间的自对准，从而提高这些电极的对准精度。由此，可以提供制造高精度廉价的场效应晶体管的方法。版权所有（C）2010，JPO＆INPIT

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