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1. 发明专利

JPH02246150A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, ITS FORMATION AND APPARATUS FOR PRODUCING IT 失效
公开(公告)号：JPH02246150A
公开(公告)日：1990-10-01
申请号：JP6584889
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MURATA JUN , TADAKI YOSHITAKA , KANEKO HIROKO , SEKIGUCHI TOSHIHIRO , UCHIYAMA HIROYUKI , NAKAMURA TAKASHI , MAEDA TOSHIO , KASAHARA OSAMU , ENAMI HIROMITSU , OGISHIMA JUNJI , NAGAO MAKI , FUNAHASHI TOMOMASA , KIGUCHI YASUO , KOJIMA MASAYUKI , KOIKE ATSUYOSHI , MIYAZAWA HIROYUKI , SADAOKA MASATO , KADOTA KAZUYA , CHIGAWARA TADASHI , NOJIRI KAZUO , KOBAYASHI YUTAKA
IPC分类号： H01L27/04 , H01L21/027 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To increase a charge storage amount of a capacity element, for information storage use, of a stacked structure and to enhance an alpha-ray soft-error breakdown strength and an integration density of a DRAM by a method wherein a correction pattern which increases a surface area of a lower-layer electrode layer is formed on the lower-layer electrode structure of the capacity element, for information storage use, of the stacked structure of a memory cell of the DRAM. CONSTITUTION:A capacity element C, for information storage use, of a memory cell M is constituted in such a way that a lower-layer electrode layer 33, a dielectric film 34 and an upper-layer electrode layer 35 are laminated one after another. The capacity element C for information storage use is constituted in a so-called stacked structure. In the lower-layer electrode layer 33, a correction pattern 33A protruding in a plane direction from a region formed in a plane square shape is formed on the connection side of an n-type semiconductor region 28 and a complementary data line 50. A size of an etching mask used to process the lower-layer electrode layer 33 is reduced by reflected light; accordingly, a size of the lower-layer electrode layer 33 is made smaller than a preset value. Then, the correction pattern 33A is constituted in such a way that the size of the lower-layer electrode layer 33 is made large in anticipation of a reduced portion of the size.

2. 发明专利

JPH08241971A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241971A
公开(公告)日：1996-09-17
申请号：JP6474696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MURATA JUN , TADAKI YOSHITAKA , KANEKO HIROKO , SEKIGUCHI TOSHIHIRO , UCHIYAMA HIROYUKI , NAKAMURA TAKASHI , MAEDA TOSHIO , KASAHARA OSAMU , ENAMI HIROMITSU , OGISHIMA JUNJI , NAGAO MAKI , FUNAHASHI TOMOMASA , KIGUCHI YASUO , KOJIMA MASAYUKI , KOIKE ATSUYOSHI , MIYAZAWA HIROYUKI , SADAOKA MASATO , KADOTA KAZUYA , CHIKAWAHARA TADASHI , NOJIRI KAZUO , KOBAYASHI YUTAKA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which reduces a short channel effect and which enhances a DRAM integration degree further by a method wherein protrusion parts are formed in parts to be used as gate electrodes of word lines used as the gate electrodes of MISFET's and the width and the interval of the respective gate electrodes are formed to be larger than the width and the interval of word lines on a field insulating film. CONSTITUTION: Word lines 26 connect respective gate electrodes 26 of MISFET's Qs's for selection of a plurality of memory cells M. In the word lines 26, protrusion parts 26A are formed on the side of other adjacent word lines 26 along the shape of the memory cells. The protrusion parts 26A are used substantially as gate electrodes of the MISFET's Qs's for selection of the memory cells, and a gate length size is made long as compared with the interconnection size of the word lines 26. In addition, an isolation size on an insulating film (a field insulating film) 23 for element isolation can be ensured sufficiently as compared with an isolation size A between the word lines 26 when the interconnection size of the word lines 26 is prescribed simply by the gate length size of the MISFET's Qs's for selection of the memory cells.

3. 发明专利

JPH08241970A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241970A
公开(公告)日：1996-09-17
申请号：JP6474596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MURATA JUN , TADAKI YOSHITAKA , KANEKO HIROKO , SEKIGUCHI TOSHIHIRO , UCHIYAMA HIROYUKI , NAKAMURA TAKASHI , MAEDA TOSHIO , KASAHARA OSAMU , ENAMI HIROMITSU , OGISHIMA JUNJI , NAGAO MAKI , FUNAHASHI TOMOMASA , KIGUCHI YASUO , KOJIMA MASAYUKI , KOIKE ATSUYOSHI , MIYAZAWA HIROYUKI , SADAOKA MASATO , KADOTA KAZUYA , CHIKAWAHARA TADASHI , NOJIRI KAZUO , KOBAYASHI YUTAKA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which reduces a disconnection defect or the like in the stepped part of the interconnection of a word line for a shunt by a method wherein a memory cell in a first region and a memory cell in a second region are connected by a common gate electrode in such a way that respective word lines are connected across both regions and a conductive layer which is the same layer as the electrode of a capacitance element is formed across both regions. CONSTITUTION: MISFET's Qs's for memory selection of a plurality of memory cells M are constituted on the main face part of p-well regions 22, and they are constituted mainly of the p-well regions 22, of gate insulating films 25, of gate electrodes 26 and of one pair of n-type semiconductor regions 28 as a source region and a drain region. The gate electrodes 26 and word lines 26 are formed respectively of the same conductive layer, and the word lines connect the respective gate electrodes 26 of the MISFET's for Qs's for memory selection of the plurality of memory cells M arranged in the row direction. In addition, n-type semiconductor regions 28 on the connection side of capacitance elements C, for information storage, of the MISFET's Qs's for memory selection are constituted integrally with n semiconductor regions 33A.

4. 发明专利

JPH01298758A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01298758A
公开(公告)日：1989-12-01
申请号：JP12839588
申请日：1988-05-27
申请人： HITACHI LTD
发明人： KANEKO HIROKO
IPC分类号： H01L21/3205 , H01L21/31 , H01L21/822 , H01L27/04 , H01L27/108
摘要： PURPOSE:To suppress the formation of a spontaneous oxide film on a polycrystalline silicon electrode and to reduce the thickness of an insulating film by forming a conductive layer on a capacity lower layer electrode by a sputtering method, and then forming the insulating layer and a capacity upper layer electrode on the conductive layer. CONSTITUTION:A conductive film is formed on a whole semiconductor substrate 1 by sputtering technique on a capacity lower layer electrode 9, and an unnecessary part is selectrively etched to form a conductive layer 10. As the conductive film, a film made of titanium nitride or titanium oxide is, for example, employed. Then, an insulating film is formed on the whole substrate 1. The insulating film is formed, for example, of a 2-layer film of an Si3N4 film obtained by a CVD technique and an SiO2 film obtained by thermally oxidizing the Si3N4 film. then, polycrystalline silicon is formed on the whole substrate 1, which is reduced in its resistance by ion implanting phosphorus or arsenic, and an unnecessary part is selectively etched to form a capacity insulating film 11 and a capacity upper layer electrode 12. Thus, the thickness of the insulating film can be substantially reduced.

5. 发明专利

JPH01243452A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01243452A
公开(公告)日：1989-09-28
申请号：JP6944688
申请日：1988-03-25
申请人： HITACHI LTD
发明人： KANEKO HIROKO , SAGAWA MASAKAZU , SUWAUCHI NAOKATSU
IPC分类号： H01L29/43 , H01L21/28 , H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To prevent the increase of the resistance value of a wiring composed of an aluminum film, and to increase the operation speed of a device by connecting the wiring to a semiconductor region through interposition of a metallic film obviating precipitation in the aluminum film of the main component of a substrate. CONSTITUTION:In a device with a wiring 17 consisting of an aluminum film connected to a semiconductor region 13 in the main surface of a semiconductor substrate 1, the wiring 17 is connected to the semiconductor region 13 while interposing a metallic film (a titanium nitride film, etc.) 14C preventing precipitation into the aluminum film 17 of the main component, silicon, of the substrate 1. Consequently, silicon as the principal component of the semiconductor substrate 1 is not precipitated into the wiring 17 made up of the aluminum film. Accordingly, the increase of the resistance value of the wiring is obviated, and the working speed of the semiconductor integrated circuit device is accelerated.

6. 发明专利

JPS6298642A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6298642A
公开(公告)日：1987-05-08
申请号：JP23729985
申请日：1985-10-25
申请人： HITACHI LTD
发明人： KANEKO HIROKO , KOYANAGI MITSUMASA
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L29/45 , H01L29/49
摘要： PURPOSE:To improve the integration degree of an IC by a method wherein the barrier metals to be formed between the semiconductor regions and the conductive layers consist of the high-melting point metal silicide layers formed on the regions in the self-matching manner and the high-melting point metal nitride layers formed in the connecting holes. CONSTITUTION:Titanium silicide TiSi layers 9 having a comparatively larger resistance, formed on upper surfaces of semiconductor regions 7b in a self- matching manner, are further annealed to be formed into titanium silicide TiSi2 layers having a small resistance and titanium silicide layers (first conductive layers) having a small resistance are formed on the upper surfaces of the semiconductor regions 7b in a self-matching manner. Moreover, after being formed on the semiconductor regions 7b in a self-matching manner, the titanium silicide layers are annealed in nitrogen-containing gas to be formed into titanium nitride layers 12. As a result, barrier metals (second conductive layers) consisting of the titanium nitride layers 12 can be formed on the semiconductor regions 7b without a mask-matching allowance.

7. 发明专利

JPS61150216A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61150216A
公开(公告)日：1986-07-08
申请号：JP27086284
申请日：1984-12-24
申请人： HITACHI LTD
发明人： KANEKO HIROKO , KOYANAGI MITSUMASA
IPC分类号： H01L21/28
摘要： PURPOSE:To contrive to miniaturize an element preventing short circuit in a metallic siliside film by a method wherein a metallic film is formed on an Si substrate and then heat-treatment is performed thereto in temperature range of almost 400-600 deg.C. CONSTITUTION:A field oxide film 2 and a gate oxide film 3 are formed on a P-type Si substrate 1 and a gate electrode 4 is formed thereon. P-ion implanting layer 5 is formed covering whole face. Secondly a side wall 6 is formed to both side of the gate electrode 4, then a Ti film 7 is formed. Then As implanting layer 8 is formed covering whole face. Thereafter, a Ti siliside 9 is formed by siliciding the Ti film 7 on the As driving layer 8. At this time, a Ti silicide 10 is formed on the gate electrode 4, too. If low temperature at less than 600 deg.C, anealing is performed, the metallic silicide to be formed does not expand to lateral direction by means that reaction of metal, the field oxide film 2 and the side wall 6 with SiO2 and the movement of Si are suppressed.

8. 发明专利

JPS6195550A Manufacture of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造
公开(公告)号：JPS6195550A
公开(公告)日：1986-05-14
申请号：JP21619684
申请日：1984-10-17
申请人： Hitachi Ltd
发明人： KANEKO HIROKO , KOYANAGI MITSUMASA
IPC分类号： H01L29/78 , H01L21/768 , H01L21/8246 , H01L27/10 , H01L27/112
摘要： PURPOSE:To reduce a sheet resistance value by forming a thin metal layer which reacts with a silicon oxide film on a semiconductor region and forming a silicide layer through formation of a thick metal layer which does not react with silicon oxide film. CONSTITUTION:An n type impurity is doped to a semiconductor substrate 1 and semiconductor regions 6a and 6b are formed by thermal diffusion. Thereafter, a metal layer such as Ti, Pt, Pa or Hf is formed on the semiconductor region 6b, GL and field insulation film 2. Heat processing is carried out, causing the silicon oxide film to react with a metal layer such as Ti and causing the metal to react with semiconductor region 6b and GL, in order to form a conductive layer 10a. Moreover, a conductive layer 11a is formed by reaction with the gate electrode 5, word line WL and metal layer. A metal layer such as Mo, W, Ta which shows lower reaction rate with silicon than that of Ti is formed on the conductive layers 10a, 11a, side wall 12 and field insulation film 2. The conductive layers 10a, 11a are formed by heat processing and the conductive layer 10b, 11b are formed by reaction between semiconductor substrate 1 and silicon in the gate electrode 5. Thereby, a sheet resistance value can be reduced.
摘要翻译：目的：通过在半导体区域上形成与氧化硅膜反应的薄金属层，通过形成不与氧化硅膜反应的厚金属层形成硅化物层来降低薄层电阻值。构成：将n型杂质掺杂到半导体衬底1中，并且通过热扩散形成半导体区域6a和6b。此后，在半导体区域6b，GL和场绝缘膜2上形成诸如Ti，Pt，Pa或Hf的金属层。进行热处理，使得氧化硅膜与诸如Ti的金属层反应导致金属与半导体区域6b和GL反应，以便形成导电层10a。此外，通过与栅电极5，字线WL和金属层反应形成导电层11a。在导电层10a，11a，侧壁12和场绝缘膜2上形成诸如Mo，W，Ta的与硅相比显示出比硅低的反应速率的金属层。导电层10a，11a由热处理和导电层10b，11b通过半导体衬底1和栅电极5中的硅之间的反应形成。由此，可以减小薄层电阻值。

9. 发明专利

JPH04162666A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04162666A
公开(公告)日：1992-06-08
申请号：JP28701790
申请日：1990-10-26
申请人： HITACHI LTD
发明人： KANEKO HIROKO , MURATA JUN
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To enable reduction in electric charge accumulation capacity of a lamination capacitor (STC) to be restricted by setting an impurity concentration of a lower-layer capacity electrode so that a part closer to a capacitive insulating film is not depleted when storing high-level information in a capacitive element. CONSTITUTION:A lower-layer electrode 10a is connected to an N -type diffusion layer 12 which is formed on a semiconductor substrate 2 electrically in a 4M-bit DRAM. The layer 12 is a semiconductor region for joining with an electrode 10a and n-type impurities such as for example phosphor are introduced into the semiconductor substrate 2. Phosphor and arsenic are introduced into for example a polycrystal Si at the electrode 10a and an impurities concentration is set to for example 3X10 -10 /cm so that a part closer to an insulating film 11 may not be depleted when writing 'H' information into a STC 6. Therefore, since an upper layer of the lower-layer electrode 10a is not depleted when writing the 'H' information, reduction of accumulation capacity caused by depletion can be restricted.

10. 发明专利

JPS61137367A Manufacture of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造
公开(公告)号：JPS61137367A
公开(公告)日：1986-06-25
申请号：JP25914484
申请日：1984-12-10
申请人： Hitachi Ltd
发明人： KOYANAGI MITSUMASA , KANEKO HIROKO
IPC分类号： H01L29/78 , H01L21/285 , H01L21/321 , H01L21/3213 , H01L29/45 , H01L29/49
CPC分类号： H01L21/32134 , H01L21/28518 , H01L21/3211 , H01L29/456 , H01L29/4933
摘要： PURPOSE: To integrate an IC by coating a titanium silicide layer when forming a barrier metal on a region for preventing aluminum for forming signal wirings and power source wirings from diffusing in a semiconductor region, and annealing in N
2 gas to form a titanium nitride layer, thereby eliminating a mask alignment.
CONSTITUTION: A thick field insulating film 2 is formed with a P
+ type channel stopper region 3 laid on the periphery of a P
- type Si substrate 1, and a polycrystalline Si gate electrode 5 is formed through a gate insulating film 4 at the center of the surface of the substrate 1 surrounded by the film 2. Then, the side wall of the electrode 5 is coated by an insulating film 6, P ions are first implanted to form a deep N
+ type source and drain regions 7b, and As impurity is then diffused to form shallow N
- type source and drain regions 7a for coupling them. Then, titanium silicide layers 9, 8 are coated only on the region 7b and the electrode 5, heat treated in N
2 gas to alter to titanium nitride layers 12, 11. Thus, a barrier metal is formed in a self-aligned manner.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在形成用于防止铝形成信号布线和电源布线的区域中形成阻挡金属的区域上涂覆硅化钛层，以在半导体区域中扩散，并且在N 2气中退火以形成氮化钛层，来集成IC，从而消除了掩模对准。构成：在P型Si基板1的周围形成有P +型沟道截止区域3的厚场绝缘膜2，通过栅极绝缘膜形成多晶硅栅电极5 在由膜2包围的基板1的表面的中心处形成4个。然后，用绝缘膜6涂覆电极5的侧壁，首先将P离子植入以形成深N +型源，漏极区域7b，然后As杂质扩散以形成用于耦合它们的浅N +型源极和漏极区域7a。然后，将硅化钛层9,8仅涂覆在区域7b和电极5上，在N2气中进行热处理以改变氮化钛层12,11。于是，以自对准的方式形成阻挡金属。

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