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1. 发明专利

JPH03228335A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH03228335A
公开(公告)日：1991-10-09
申请号：JP2200090
申请日：1990-02-02
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI VLSI ENG
发明人： SHIBA TAKEO , OGIWARA ITARU , TAMAOKI YOICHI , SHIMAMOTO HIROMI , KOBAYASHI TAKASHI , NANBA MITSUO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L27/082 , H01L29/732
摘要： PURPOSE:To reduce the specific resistance and the parasitic resistance of a polycrystalline silicon electrode in a bipolar transistor by using polycrystalline silicon with a grain size above a specific value for the polycrystalline silicon electrode of base, emitter, or collector. CONSTITUTION:In a vertical bipolar transistor consisting of a conductivity-I first layer 2 provided in a semiconductor substrate 1, a conductivity-II second layer 7 provided on it, and a conductivity-I third layer 8 provided further on it, electrodes 5, 10 made of polycrystalline silicon film are connected to the first layer 2, second layer 7, or third layer 8, so that the largest side of its polycrystalline silicon grain is 1mum or larger. For example, amorphous silicon layers are deposited, injected with impurity atoms, and heat-treated at 900 deg.C or higher temperature, thus forming base electrodes 5 and emitter electrodes 10 consisting of polycrystalline silicon with a grain size of 2mu or larger. Thereafter, a passivation film 11 is deposited to form base, emitter, and collector metal electrodes 12, 14.

2. 发明专利

JPS62189753A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62189753A
公开(公告)日：1987-08-19
申请号：JP3088686
申请日：1986-02-17
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OGAWA TETSUO , SHIBA TAKEO , NANBA MITSUO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To accelerate the operation of a semiconductor device by partly forming a connector of a polycrystalline Si electrode with a single crystal element forming region in an Si COS structure to reduce a junction capacity, to increase an active region and to improve the dimensional accuracy. CONSTITUTION:High density base regions 25' are formed on the left side portion of a base region 15, on front and back portions perpendicular to the paper, i.e., on the three of four surfaces of the periphery of an active region. This bipolar transistor is insulated by forming an oxide film 204 on part of a connector for connecting a base region 25 with a base leading polycrystalline Si electrode 27 to reduce the ratio of the region 25' to the active region of the transistor. Thus, the ratio of the active base region to the area of the emitter can be effectively increased, and a junction capacity between the base and the collector can be reduced.

3. 发明专利

JPH053204A SEMICONDUCTOR DEVICE RESISTANT TO ALPHA-RAY, INTEGRATED CIRCUIT, AND LOGIC CALCULATION DEVICE 失效
公开(公告)号：JPH053204A
公开(公告)日：1993-01-08
申请号：JP15436691
申请日：1991-06-26
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NAKAMURA TORU , ONOUCHI YUKIHIRO , SHIBA TAKEO , TAMAOKI YOICHI , NANBA MITSUO , WASHIO KATSUYOSHI , SHIMAMOTO HIROMI , TANABE MASAMICHI , HONMA NORIYUKI
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/082 , H01L29/73 , H01L29/732
摘要： PURPOSE:To provide a transistor structure capable of ultrahigh speed operation while preventing malfunctions such as soft errors so as to improve the reliability of ULSIs and large computers. CONSTITUTION:A transistor composed of a first region (101), a second region (102), and a third region (103) has at least one silicon part including an intrinsic region. The silicon part is bent in a plane or cross section. Therefore, the transistor having the bent structure is irradiated only at a small part with alpha-rays that tend to advance straight. The charge produced by a-ray irradiation is smaller as compared with the transistor's capacitance, and thus it is possible to prevent malfunction and realize ultrahigh speed operation.

4. 发明专利

JPH04152564A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04152564A
公开(公告)日：1992-05-26
申请号：JP27623690
申请日：1990-10-17
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBA MITSUO , NAKAZATO KAZUO , NAKAMURA TORU , SHIMAMOTO HIROMI , WASHIO KATSUYOSHI , ISHIKAWA MICHIO , WAKIMOTO EIJI , TANIZAKI YASUNOBU
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To materialize single crystal Si high resistance and improve the depen dency on bias by forming the surface concentration and the junction depth of a resistance layer in specified condition area. CONSTITUTION:For a semiconductor device, which has p-type single crystal Si high resistance, an aperture area is provided in the desired position of the insulating film 2 provided at the surface of an n-type semiconductor substrate 1, and an electrode 3 is made. P-type junction 4 is a resistance layer. And the surface concentration Co [cm ] and the junction depth Xj [mum] are formed in the condition area surrounded by the relation formula (I), and sheet resistance rhos=2.5-100[kpi/squ.], temperature property = 0.50[%/DELTAT[ deg.C]] or less, and temperature at which temperature dependency coefficient is converted from negative to positive = 0[ deg.C] or less.

5. 发明专利

JPH04145657A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04145657A
公开(公告)日：1992-05-19
申请号：JP26836090
申请日：1990-10-08
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： SHIMAMOTO HIROMI , NAKAMURA TORU , NANBA MITSUO , WASHIO KATSUYOSHI
IPC分类号： H01L27/04 , H01L21/822 , H01L23/58
摘要： PURPOSE:To provide a resistance element having arbitrary temperature characteristic without limiting the value of a specific resistance and to facilitate temperature compensation of a resistance value in design of a circuit by connecting resistors each having different temperature dependence in parallel. CONSTITUTION:A resistor is formed of a substrate 1 provided in a P-type silicon substrate 1, an N-type diffused layer 5 as a reverse conductivity type impurity layer and a P-type polycrystalline silicon layer 4a having reverse temperature dependency of a resistance to that of the layer 5 as a parallel resistance circuit. That is, the resistors having different temperature dependences are connected in parallel to form a resistance having small temperature dependence. The resistors having different temperature dependences are connected in parallel in a using temperature range to be an object to obtain the resistors having arbitrary temperature dependence, thereby approaching the temperature dependence to zero. Thus, since the resistor having small temperature dependence, the resistor having arbitrary temperature dependence can be formed without limit the value of the specific resistance, the temperature compensation of the resistance value can be facilitated.

6. 发明专利

JPH03147368A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03147368A
公开(公告)日：1991-06-24
申请号：JP28298989
申请日：1989-11-01
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： SHIMAMOTO HIROMI , NAKAMURA TORU , SHIBA TAKEO , NANBA MITSUO , ONOUCHI YUKIHIRO , HONMA NORIYUKI , IKEDA SEIJI , SAGARA KAZUHIKO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8229 , H01L27/102 , H01L29/47 , H01L29/732 , H01L29/872
摘要： PURPOSE:To decrease series resistance and to obtain a fine semiconductor device resistant to the soft errors by external noise or alpha rays by taking out a cathode electrode from the periphery of an anode. CONSTITUTION:A contact hole for cathode is made in a ring shape using potoetching technology on a silicon dioxide 21. After this, polycrystalline silicon 8 is made to cover the contact hole, and is doped with phosphorus, and is heat- treated to form an N-type diffusion layer 11. After this, silicon dioxide 10 is provided, and contact holes for an anode and others are made at silicon dioxides 6 and 21. Hereupon, the contact hole for an anode is located inside the contact hole for a cathode, and is arranged so that the distance between both contact holes may be equal. Next, a silicide layer 14 is provided at the surface of the anode. After this, an Al electrode is made, and a semiconductor device, which is great in resistance to external noise and small in series resistance, is realized.

7. 发明专利

JPH0822994A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0822994A
公开(公告)日：1996-01-23
申请号：JP15557894
申请日：1994-07-07
申请人： HITACHI LTD
发明人： NANBA MITSUO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732
摘要： PURPOSE:To realize fine structure of a bipolar transistor constituting a semiconductor integrated circuit device. CONSTITUTION:In a bipolar transistor wherein a base region 3, an emitter region 4 and a collector leading-out region 2 are formed on a semiconductor substrate, a base connection part 3a for leading out a base electrode is formed in the base region 3, an emitter connection part 4b for leading out an emitter electrode is formed in the emitter region 4, and a collector connection part for leading out a collector electrode is formed in the collector leading-out region 2, the base connection part 3a and the collector leading-out region 2 are arranged on the same straight line.

8. 发明专利

JPH05166825A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05166825A
公开(公告)日：1993-07-02
申请号：JP33326391
申请日：1991-12-17
申请人： HITACHI LTD
发明人： NANBA MITSUO , MORI HIROSHI , ISHIKAWA MICHIO , WAKIMOTO EIJI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732
摘要： PURPOSE:To prevent the deterioration of an emitter/base junction so as to improve the reliability by setting the impurity concentration in the region above the depth of an emitter junction higher than that in the region within the emitter junction forming depth from the surface of a semiconductor. CONSTITUTION:The peak value of the concentration in a first base layer 2 is in the region within the emitter junction forming depth from the surface of a semiconductor, and the peak value of the concentration in a second base layer 2 is in the region above the emitter junction forming depth. And, the concentration of the impurities in the region above the emitter junction forming depth is higher than that in the region within the emitter junction forming depth. Accordingly, the intensity of an electric field can be reduced by the improvement of a base profile. Hereby, the generation of hot carriers is suppressed, and the life of a device improves sharply. What is more, the application of the stress voltage higher than before becomes possible, and the improvement of the speed of a circuit becomes possible.

9. 发明专利

JPH03211276A VACUUM TREATING DEVICE 失效
公开(公告)号：JPH03211276A
公开(公告)日：1991-09-17
申请号：JP611290
申请日：1990-01-17
申请人： HITACHI LTD
发明人： NANBA MITSUO , EZAKI SHINOBU
IPC分类号： C23C14/54 , C23C14/56
摘要： PURPOSE:To continuously treat a work in a vacuum state by providing a means for detecting a slit-shapes sealing spacing, etc., and utilizing the attraction force of an electromagnet by the signal from this means, by which the slit spacing can be adjusted. CONSTITUTION:This vacuum treating device is disposed with prevacuum chambers 2, 3 on the front and rear sides of a vacuum treating chamber 1. The treating device is sealed continuously from the outside by a sealing device 13 at the time when the work F is transported. The means 6 for detecting the film thickness of the work is provided on the feed side and the thickness of the work F is detected. A control means is operated by the detection signal thereof and the spacing of the above-mentioned sealing device 13 is adjusted by the attraction force of the electromagnet 15. A position detecting means 14 which detects the spacing of this sealing device is provided and the spacing is so controlled that always the prescribed seal spacing is attained.

10. 发明专利

JPS62195173A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62195173A
公开(公告)日：1987-08-27
申请号：JP3524186
申请日：1986-02-21
申请人： HITACHI LTD
发明人： SHIBA TAKEO , NANBA MITSUO , NAKAMURA TORU , NAKAZATO KAZUO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To reduce the ratio of the transit time of carriers in graft base regions to the total transit time of carriers in an SICOS type bipolar transistor by a method wherein inclinations spreading toward the depth direction are provided on the side walls of a single crystal semiconductor layer which is contacted with nonactive base regions. CONSTITUTION:After an n type buried layer 4 is formed in a p-type Si substrate, 1 an n-type Si epitaxial layer 3 and, selectively, Si oxide films 5 are formed. The layer 3 is etched with the oxide films 5 as masks to form isolation trenches 2. At that time, inclinations spreading toward the depth direction are provided on the side walls 30 of the layer 3. After Si oxide films 8 are formed on the parts of the side walls 30 of the layer 3 and Si oxide films 6 are formed in the isolation trenches 2, a polycrystalline Si layer 7 is deposited over the whole surface. After the layer 7 is doped with a p-type impurity, the layer 7 is removed by etching except nonactive base regions 9. After that a hot oxide film 10 is formed. Then a p-type impurity is diffused into the layer 3 by hot diffusion to form graft base regions 11. Then a p-type active base region 12, an n-type emitter region 14, an n-type collector region 13 and electrodes 15 are formed.

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