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1. 发明专利

JPH04152564A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04152564A
公开(公告)日：1992-05-26
申请号：JP27623690
申请日：1990-10-17
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBA MITSUO , NAKAZATO KAZUO , NAKAMURA TORU , SHIMAMOTO HIROMI , WASHIO KATSUYOSHI , ISHIKAWA MICHIO , WAKIMOTO EIJI , TANIZAKI YASUNOBU
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To materialize single crystal Si high resistance and improve the depen dency on bias by forming the surface concentration and the junction depth of a resistance layer in specified condition area. CONSTITUTION:For a semiconductor device, which has p-type single crystal Si high resistance, an aperture area is provided in the desired position of the insulating film 2 provided at the surface of an n-type semiconductor substrate 1, and an electrode 3 is made. P-type junction 4 is a resistance layer. And the surface concentration Co [cm ] and the junction depth Xj [mum] are formed in the condition area surrounded by the relation formula (I), and sheet resistance rhos=2.5-100[kpi/squ.], temperature property = 0.50[%/DELTAT[ deg.C]] or less, and temperature at which temperature dependency coefficient is converted from negative to positive = 0[ deg.C] or less.

2. 发明专利

JPH02250330A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH02250330A
公开(公告)日：1990-10-08
申请号：JP7061389
申请日：1989-03-24
申请人： HITACHI LTD
发明人： WAKIMOTO EIJI
IPC分类号： H01L29/73 , H01L21/331
摘要： PURPOSE:To easily control a base width by a method wherein, even in a horizontal-type transistor by a diffusion from a sidewall with reference to a mesa-shaped active region, a base part and an emitter part are formed by a double diffusion. CONSTITUTION:One part in one main face of a semiconductor substrate is etched to form a mesa; polycrystalline silicon parts 2, 3 are brought into contact with both side faces of this mesa part 1; a base layer 5 and an emitter layer 4 are formed by a double diffusion from one side face and a layer 7 used to reduce a collector resistance is formed by a diffusion from the other side face by making use of the mesa part as a diffusion source. In this case, a mutual positional relationship between the base layer 5 and the emitter layer 4 in the semiconductor mesa part 1 is decided mainly by a heat treatment for the double diffusion from one side face and has nothing to do with a width of the mesa part. Thereby, it is possible to decide a base width with high accuracy without being influenced by photolithography.

3. 发明专利

JPH03286561A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03286561A
公开(公告)日：1991-12-17
申请号：JP8892090
申请日：1990-04-03
申请人： HITACHI LTD
发明人： WAKIMOTO EIJI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8222 , H01L27/06 , H01L29/47 , H01L29/872
摘要： PURPOSE:To enable characteristics of a Schottky barrier diode element to be improved and life of a capacitive element to be extended by connecting a wire to an anode region of the Schottky barrier diode element, by forming a second electrode on a dielectric film through a second opening, and by forming a capacitive element. CONSTITUTION:When performing sputter etching to the surface of a cathode region 2 of a Schottky barrier diode element SBD, the surface of a dielectric film 20 of a capacitive element C is covered with a passivation film 10. and wet etching is used in that no damage is caused on this dielectric film, or a second opening which is formed on the dielectric film of the passivation film does nearly cause damage to the dielectric film, thus preventing the dielectric film of the capacitive element from being damaged during production process. As a result, the Schottky barrier diode element performs sputter etching on a surface of the cathode region, secures safety of characteristics, and the dielectric film of the capacitive element does not deteriorate greatly, thus achieving a longer life.

4. 发明专利

JPS63293978A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS63293978A
公开(公告)日：1988-11-30
申请号：JP12828087
申请日：1987-05-27
申请人： HITACHI LTD
发明人： WAKIMOTO EIJI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/417 , H01L29/72 , H01L29/732
摘要： PURPOSE:To miniaturize a collector electrode, to allow for the space of elements and to facilitate a layout by leading out an electrode from an n diffusion layer as an emitter by utilizing a hole for diffusing the emitter as it is and leading out an electrode from the n diffusion layer for a collector by making the electrode smaller than a hole for diffusing the collector. CONSTITUTION:A p-type diffusion layer 8 formed to the surface of a section (the upper section of a step) to which a groove in an island region is not shaped is used as a base for an n-p-n transistor, and an n diffusion layer 9 as an emitter is formed to the partial surface of the base 8. An n diffusion layer 11 for a collector is shaped to the lower section of the step of the island region. A hole in an SiO2 film bored for forming the emitter n diffusion layer 9 is covered completely with an emitter Al electrode 10e connected to the emitter n diffusion layer 9. A collector Al electrode 10c is brought into contact in the narrow section of the surface of the collector n diffusion layer 11. The collector leading-out electrode loc can be connected by a small contact section to the n diffusion layer 11, thus forming an electrode pattern in small size the same as base-emitter electrodes.

5. 发明专利

JPS62276855A ELECTRONIC DEVICE PROTECTIVE TOOL AND MOUNTING METHOD FOR ELECTRONIC DEVICE BY USING THE SAME 失效
公开(公告)号：JPS62276855A
公开(公告)日：1987-12-01
申请号：JP11921886
申请日：1986-05-26
申请人： HITACHI LTD
发明人： WAKIMOTO EIJI
IPC分类号： H01L23/00 , H01L23/60
摘要： PURPOSE:To reduce electrostatic breakdown, by equipping a positioning part, which is made to adhere to one main surface of an electronic device package capable of being freely assembled/disassembled, and a conductor, one part of which is connected with the positioning part and the other part of which is brought in contact with external connection terminals in the electronic device. CONSTITUTION:A positioning part 2 is formed of a flat plate adhesive tape or the like so that it is formed in conformity with a shape of an IC package 12. An elastic and conductible material such as a sponge containing carbon or the like is formed into a frame shape capable of being in contact with external connection terminals 13, so that an electronic device protective tool 1 nearly of a liquid measure shape is formed of the positioning part 2 and the conductor 3. In incorporating an electronic device 11 with it, the frame-shaped conductor 3 is coupled with the package 12 so that it can be brought in contact with the external connection terminals 13 in the electronic device 11 and the positioning part 2 can be made to adhere with adhesive force to one main surface of the package 12. The external connection terminals 13 of the electronic device 11 are thus kept equipotential through the conductor. 3, and hence no potential difference due to static electricity occurs to reduce electrostatic breakdown of the electronic device 11.

6. 发明专利

JPS62111459A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62111459A
公开(公告)日：1987-05-22
申请号：JP25076285
申请日：1985-11-11
申请人： HITACHI LTD
发明人： WAKIMOTO EIJI
IPC分类号： H01L27/04 , H01L21/331 , H01L21/822 , H01L27/06 , H01L29/72 , H01L29/73
摘要： PURPOSE:To obtain an MIS capacitor having excellent surface efficiency without increasing processes so much, by forming a conductor film on a diffused layer, which is formed on the surface of a substrate at the same time of forming an emitter, through a dielectric film. CONSTITUTION:An n layer 2 is embedded in a p type Si substrate 1, and an epitaxial n layer 3 is grown. A (p) isolating layer 4 is formed. A thick oxide film 5, which is to become a field port, is formed. With a photoresist film 6 and an oxide film 5 as masks, B ions are implanted. A PSG film 7 is formed. After a base (p) layer 8 is formed, emitter photoetching is performed. At the same time, the PSG film and the oxide film at the collector part of an n-p-n transistor and an MIS capacitor part are removed. As ions are implanted. Then a dielectric film 9 is grown on the entire surface. A part of the dielectric film is removed and emitter annealing is performed. An emitter n layer 10 and a collector n layer 11 of the n-p-n transistor are formed. Both electrodes 12 of an Al wiring and the MIS capacitor which are ohmic-contacted with the regions of the emitter part, the collector part and the MIS capacitor are formed.

7. 发明专利

JPH1187614A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1187614A
公开(公告)日：1999-03-30
申请号：JP24404597
申请日：1997-09-09
申请人： HITACHI LTD
发明人： WAKIMOTO EIJI
IPC分类号： H01L27/04 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To suppress the fault of a capacitor element, by constituting at least one electrode of the element by a plurality of conductive plates insulation- isolated from one another, and connecting the plurality of the plates in parallel via a fuse element. SOLUTION: A capacitor element C is constituted by a laminated structure obtained by sequentially laminating an electrode, dielectric film and other electrode 6 on a surface of a field insulating film. The electrode 6 is formed, for example, of three conductive plates 6A, 6B and 6C. The plates 6A, 6B and 6C are formed in a first wiring layer, insulation-isolated from each other and connected in parallel via wirings 10, 8. A fuse element F is inserted into a wiring route between the plate 6A and the wiring 8. A fuse element F is inserted into a wiring route between the plate 6B and the wiring 8, and a fuse element F is inserted into a wiring route between the plate 6C and the wiring 8.

8. 发明专利

JPH1187613A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1187613A
公开(公告)日：1999-03-30
申请号：JP24404497
申请日：1997-09-09
申请人： HITACHI LTD
发明人： WAKIMOTO EIJI
IPC分类号： H01L27/04 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To prevent a short circuit between electrodes of a capacitor element, by providing an insulating film fluidized at lower temperature than that of electrodes of the element between the electrode and a dielectric film. SOLUTION: A capacitor element C has a laminated structure obtained by sequentially laminating an electrode 3, dielectric film 5 and electrode 7 on a surface of a field insulating film 2, and a large capacity of, for example, several hundreds [pF]. An insulating film fluidized at lower temperature than those of the electrodes 3, 7 is provided between the electrode 7 and the film 5 of the element C. A film 6 is formed of a BPSG film deposited, for example, by a CVD method. Since the BPSG film is changed at glass transition temperature, i.e., fluidizing temperature according to implanting amounts of boron (B) and phosphorus (P), the BPSG film can be fluidized at lower temperature than those of the electrodes 3, 7 made of a polycrystalline silicon films in which boron is implanted by controlling the implanting amounts of boron (B) and phosphorus (P).

9. 发明专利

JPS6329585A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6329585A
公开(公告)日：1988-02-08
申请号：JP17158086
申请日：1986-07-23
申请人： HITACHI LTD
发明人： WAKIMOTO EIJI
IPC分类号： H01L29/73 , H01L21/331 , H01L27/08 , H01L29/72 , H01L29/732
摘要： PURPOSE:To form a bipolar npn transistor as well as a longitudinal pnp transistor in high hFE and fr on a substrate by a method wherein a p type diffused layer formed on a part of surface of an n type semiconductor is assumed as an emitter while a p type buried layer is assumed as a collector. CONSTITUTION:Grooves 5 0.8-1.0 mum deep are made in a part of isolation part, regions I, II by photoetching an epitaxial layer 2. Next, a part of grooves is implanted with B ion using the photoresist as a mask; and simultaneously a collector pick up p layer is formed on the surface of groove in the region II. Finally, the parts not formed into the grooves 5 are implanted with B ion using the newly formed photoresist as a mask to perform diffusion process (so-called BR layer diffusion) and then a base p layer is formed in the region I simultaneously to form an emitter p layer in the region II.

10. 发明专利

JPS62111461A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62111461A
公开(公告)日：1987-05-22
申请号：JP25076185
申请日：1985-11-11
申请人： HITACHI LTD
发明人： WAKIMOTO EIJI , TANIZAKI YASUNOBU
IPC分类号： H01L21/265 , H01L21/8226 , H01L27/082
摘要： PURPOSE:To implement highly integrated, high-speed IIL, in a process, wherein a linear part and injected integration logic (IIL) are commonly provided on the surface of one semiconductor substrate, by intactly utilizing a color-part etching mask, performing high-concentration diffusion, thereby narrowing the color part. CONSTITUTION:On an Si substrate 1, an HLD (deposited at a high temperature and at a low pressure) SiO2 film 4 is grown on the surface of an epitaxial n layer 3, which is formed through an n embedded layer 2 that is to become an emitter. The HLD film is etched by photolithography, and a window of a color part 5 is provided. With the HLD film 4, in which the window is formed, as a mask, the surface of silicon n layer undergoes dry etching with CF gas and the like, and a color groove 6 is formed. Then, with said HLD film 4 as a mask, donor impurities, e.g., phosphorus ions are implanted in the bottom of the color groove. Thereafter, with an SiO2 film 7 formed by surface oxidation as a mask, impurity ions are selectively implanted. By diffusion, an injector (p) layer 8, a base (p) layer 9 and a collector n layer 10 are formed. The impurities, which are injected beneath the groove 6 of the color part by the thermal diffusion during this time, are elongated, and an n type high concentration region 11, which is connected to the n embedded layer 2, is formed.

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