会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明专利
    • INPUT/OUTPUT OPERATION SIMULATION SYSTEM
    • JPH04148438A
    • 1992-05-21
    • JP27225490
    • 1990-10-12
    • HITACHI LTD
    • WATANABE HIDEO
    • G06F13/10G06F11/26G06F11/32
    • PURPOSE:To simulate an operation equivalent to that on a target machine and to test software on input/output operation control by constituting a simulator by means of a command control function, an instruction execution function, an interruption reception function, a memory control function and a memory mechanism. CONSTITUTION:An input/output control memory 9 in the unit of an input/output command fetched after decoding an input/output instruction is provided. Interrup tion designation and the designation of a debug function such as tracing can timely by executed in an interactive system. An input/output memory control part 8 referring to the content of the input/output control memory 9 and control ling the debug function is connected between a simulation execution control part 6 and an input/output control mechanism 10 simulating an input/output control operation. Thus, the test/debug functions on input/output control can be realized without damaging the pseudo function of the input/output control operation, and the test/debug manhours of software for a micro computer accom panied by an input/output processing can be reduced.
    • 5. 发明专利
    • DATA PROCESSING SYSTEM
    • JPS5659337A
    • 1981-05-22
    • JP13417079
    • 1979-10-19
    • HITACHI LTD
    • WATANABE HIDEO
    • G06F13/12G06F3/00
    • PURPOSE:To make it possible to execute the data processing at a high speed, by controlling in parallel the transmission and receiving of a data between the terminal control unit, and the central processing unit and the terminal equipment. CONSTITUTION:When a data write command has been received from CPU7, the head address of the picture buffer 11 is set to the registers 9, 13. When the terminal adaptor 5 has read out a data of the video equipment 6, the data is written in the picture buffer 11, the contents of the register 13 are added by ''1'', and this processing is repeated. The channel adaptor 2 detects the result of comparison of the register 9 and the register 13 by the comparator 10, and in case when the contents of the register 9 are smaller than those of the register 13, the data is received from CPU, the data is written in the picture buffer 11 in accordance with the contents of the register 9, the contents of the register 9 are added by ''1'', this processing is repeated, and when all the data have been received, instructions for returning all the data to the video equipment 6 are given.