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1. 发明专利

JPH0786874A VARIABLE CAPACITY CIRCUIT AND ANALOG FILTER CIRCUIT 失效
公开(公告)号：JPH0786874A
公开(公告)日：1995-03-31
申请号：JP23009393
申请日：1993-09-16
申请人： HITACHI LTD
发明人： TANBA HIROKO , YAMAKIDO KAZUO
IPC分类号： H03H11/04 , H03H11/12
摘要： PURPOSE:To prevent the variance of the cut-off frequency despite the variance of capacity or the resistance value by using the mirror capacity seeming like double gain of an operational amplifier as the capacity of a CR filter circuit and by controlling the gain of the operational amplifier. CONSTITUTION:The mirror capacity consists of an operational amplifier 30 and a capacitor element 4' which is connected between an output terminal and an inverted input terminal of the amplifier 30. A 1st terminal T1 and a 2nd terminal T2 of a variable capacitor circuit 40 are connected to a resistor R and an AC ground potential respectively. The cut-off frequency of a CR filter circuit is shown as fc=1/2piGCR and can be kept constant by controlling the gain G of the amplifier 30 so as to set the overall apparent CR value of the circuit 40 at a prescribed level despite the variance of the capacitor value C of the element 4' included in the circuit 40. The gain of the amplifier 30 can be controlled by an existing gain control method like the control of current of a constant current source included in the amplifier 30, etc.

2. 发明专利

JPH05175803A VOLTAGE COMPARING CIRCUIT AND ANALOG/DIGITAL CONVERTER 失效
公开(公告)号：JPH05175803A
公开(公告)日：1993-07-13
申请号：JP35702491
申请日：1991-12-25
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： KUDO MASAKI , TANBA HIROKO , YAMAKIDO KAZUO
IPC分类号： H03F3/45 , H03K5/08 , H03M1/12
摘要： PURPOSE:To provide a voltage comparing circuit capable of high-speed and high-precision voltage comparing operation with a low voltage and small power consumption. CONSTITUTION:A differential amplifying circuit 4 which differentially amplifies input voltages to output complementary signals to output terminals and has a first switch circuit which can selectively short-circuit the output terminals, clocked inverters 5 and 6 which have input terminals coupled to respective output terminals of the differential amplifying circuit 4, a second switch circuit M8 which selectively short-circuits the outputs of clocked inverters 5 and 6, and latch circuits 9 and 10 which hold complementary signals outputted from clocked inverters 5 and 6 are included to constitute a voltage comparing circuit 1. Clocked inverters 5 and 6 are activated at a prescribed timing after turning- off of the first switch circuit to perform the data latch operation in latch circuits 9 and 10, and the second switch circuit M8 is turned off in the data latch operation period.

3. 发明专利

JP2003324345A Frequency divider, frequency dividing circuit, and pll circuit 审中-公开
标题翻译：频率分路器，频率分路电路和PLL电路
公开(公告)号：JP2003324345A
公开(公告)日：2003-11-14
申请号：JP2002130685
申请日：2002-05-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MARUYAMA TETSUYA , TANBA HIROKO
IPC分类号： G06F1/08 , H03K23/00 , H03K23/64 , H03L7/197
摘要： PROBLEM TO BE SOLVED: To realize a frequency divider which can have a frequency division ratio 'natural number/2' by using a simple circuit. SOLUTION: The frequency divider which can have the frequency division ratio 'natural number/2' is simplified by providing a 1st both-edge trigger type flip-flop circuit (11) which can be triggered with both leading and trailing edges of an input signal waveform to operate, a 2nd both-edge trigger type flip-flop circuit (12) which is arranged behind the 1st both-edge trigger type flip-flop circuit and can be triggered with both leading and trailing edges of the input signal waveform to operate, and a composite gate (13) which controls the frequency division ratio of the input signal according to the output signals of the 1st and 2nd both-edge trigger flip-flop circuits and a control signal. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过使用简单的电路来实现可以具有分频比“自然数/ 2”的分频器。解决方案：通过提供第一双边缘触发型触发器电路（11），能够使分频比“自然数/ 2”分频的分频器被简化，该触发器电路可以由前沿和后沿触发要操作的输入信号波形，布置在第一双边缘触发型触发器电路之后的第二双边缘触发型触发器电路（12），并且可以由输入信号的前沿和后沿触发波形操作，以及根据第一和第二双边缘触发电路的输出信号和控制信号来控制输入信号的分频比的复合门（13）。版权所有（C）2004，JPO

4. 发明专利

JP2001111421A OFFSET CANCEL CIRCUIT AND A/D CONVERTER 失效
公开(公告)号：JP2001111421A
公开(公告)日：2001-04-20
申请号：JP28506199
申请日：1999-10-06
申请人： HITACHI LTD
发明人： TANBA HIROKO
IPC分类号： H03M1/06 , H03K5/08 , H03M1/10 , H03M1/36
摘要： PROBLEM TO BE SOLVED: To provide technology for reducing offset deterioration due to a temperature change. SOLUTION: When the temperature dependency of a bias current supplied from a bias circuit 221 to an offset cancel current generation circuit 24 is set equivalent to the temperature dependency of an offset current allowed to flow into an offset canceled circuit 21, mutual conductance is changed in accordance with temperature by adjusting the offset cancel current at a certain temperature, so that the variation of an offset cancel current can be allowed to follow the variation of an offset current and offset deterioration due to a temperature change can be reduced.

5. 发明专利

JP2000165241A A/D CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2000165241A
公开(公告)日：2000-06-16
申请号：JP33265998
申请日：1998-11-24
申请人： HITACHI LTD
发明人： TANBA HIROKO
IPC分类号： G11B20/10 , H03M1/14 , H03M1/36
摘要： PROBLEM TO BE SOLVED: To obtain a parallel operation type A/D converter where a high speed operation and high precision can be realized. SOLUTION: An offset cancellation circuit 5 that detects an offset and generates a cancellation signal in response to the offset is provided independently to each voltage comparator circuit 4. The voltage comparator circuit 4 compares a signal voltage 4IN with a reference voltage 4REF and adds an inverted offset to the offset based on an offset cancellation signal 5OFC to cancel the offset of the input to the comparator circuit. A voltage division circuit 2 generates the reference voltage. Switch circuits SW1, SW2 apply a signal voltage to a reference voltage input terminal and a signal voltage input terminal of each voltage comparator circuit for an offset detection period and the voltage comparator circuit outputs a comparison result in response to the input offset. The offset cancellation circuit generates the offset cancellation signal on the basis of the comparison result.

6. 发明专利

JPH0837238A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0837238A
公开(公告)日：1996-02-06
申请号：JP19101094
申请日：1994-07-21
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： TANBA HIROKO , HASE AKIHIRO , OKAZAKI TAKAO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/088
摘要： PURPOSE:To protect the input MOSFET's in an interface unit by placing between a plurality of power supply terminals both of unidirectional elements that are provided with so high a threshold voltage as to be turned off when power is being normally supplied. CONSTITUTION:MOSFET's Q1-Q6 with a diode connected are placed between different power supply terminals VA, VD, VX. These MOSFET's Q1-Q6 are provided with so high a threshold voltage that they will not be turned on in ordinary operating condition. This allows a thick field insulating film to be used for gate insulating films; so-called parasitic MOSFET's are used. Thus, the threshold voltage of the n-type aluminum parasitic MOSFET's Q1-Q6 is used, and potential difference between independent power supplies, which may cause the electrostatic breakdown of interface elements between the independent power supplies, is thereby canceled. This avoids the electrostatic breakdown of interface elements.

7. 发明专利

JP2000188517A DIFFERENTIAL AMPLIFIER, COMPARATOR, A/D CONVERTER, SEMICONDUCTOR INTEGRATED CIRCUIT AND STORAGE DEVICE 失效
公开(公告)号：JP2000188517A
公开(公告)日：2000-07-04
申请号：JP36416898
申请日：1998-12-22
申请人： HITACHI LTD
发明人： TANBA HIROKO
IPC分类号： H03M1/36 , H03F1/22 , H03F3/45 , H03K5/08
摘要： PROBLEM TO BE SOLVED: To improve the voltage amplification gain without increase of a load impedance by providing a first load resistor where one terminal is connected to the second polarities of first and third transistors and the other terminal is connected to a first power line, connecting one terminal to the second electrodes of second and fourth transistors and the other terminal to a first power line. SOLUTION: A differential amplifier is provided with a p-type MOS transistor TP 3 which is connected in series between a power line to which first voltage VDD is applied and an installation line to which second voltage is applied. PMOSTP1 and TP2 of differential constitution, n-type MOS transistors TN1 and TN2 of the differential constitution and NMOSTN3 are also provided. PMOSTP3 where a source electrode is connected to the power line constitutes a first constant current source and constant bias voltage VGP is applied to a gate electrode. NMOSTN3 where a source electrode is connected to the installation line constitutes a second constant current source.

8. 发明专利

JPH08321584A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH08321584A
公开(公告)日：1996-12-03
申请号：JP12849895
申请日：1995-05-26
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： TANBA HIROKO , KUDO MASAKI
IPC分类号： H01L27/04 , G05F1/10 , G05F1/56 , H01L21/822 , H03F1/30
摘要： PURPOSE: To suppress distortion of signal due to fluctuation of fabrication by generating the central voltage of internal signal, serving as a reference voltage, from a second buffer amplifier connected with the gate-drain common terminal of a first conductivity type MOSFET. CONSTITUTION: A reference voltage trimming circuit 2 is connected with the output terminal of a reference voltage generation circuit 1. A filter 3 comprising a resistor R1 and a capacitor C1 is connected with the output terminal of the reference voltage trimming circuit 2 and a buffer amplifier AMP 2 having an output terminal connected with the source of a first conductivity type MOSFETM 1. The reference voltage trimming circuit 2 also has an output terminal connected with a threshold value cancel type bias circuit 4 which delivers an output voltage to the gate of the MOSFETM 1 having drain connected with a second conductivity type MOSFETM 2.

9. 发明专利

JPH07235839A VARIABLE CONDUCTANCE AMPLIFIER 失效
公开(公告)号：JPH07235839A
公开(公告)日：1995-09-05
申请号：JP2436694
申请日：1994-02-22
申请人： HITACHI LTD
发明人： TANBA HIROKO , YAMAKIDO KAZUO
IPC分类号： H03F1/02 , H03F3/45 , H03H11/04
摘要： PURPOSE:To reduce the power consumption and transmission distortion by providing a 1st circuit employing an ohmic resistive element to implement voltage/current conversion with excellent linearity and a 2nd circuit implementing variable control of a mutual conductance to the amplifier. CONSTITUTION:An input voltage Vin applied between inputs inm, imp in a 1st circuit 1 is applied between terminals of an ohmic resistive element R through the source follower operation of transistors(TRs) M1, M2. A gate voltage of TRs M3, M4 is given to gates of TRs M5, M6 of a 2nd circuit 2. Thus, the TRs M5, M6 generate a drain current in response to a drain current of the TRs M3, M4, that is, the current Tin flowing to the resistive element R. A rate of change in an output current IGmc with respect to the input voltage Vin, that is, an output mutual conductance is controlled by controlling variably a current generated from a variable current source with a control voltage Vc.

10. 发明专利

JPH07221643A ANALOG/DIGITAL CONVERTER AND PORTABLE COMMUNICATION TERMINAL EQUIPMENT USING THE SAME 失效
公开(公告)号：JPH07221643A
公开(公告)日：1995-08-18
申请号：JP3546194
申请日：1994-02-08
申请人： HITACHI LTD
发明人： TANBA HIROKO , YAMAKIDO KAZUO , FURUKAWA KATSUHIRO , OKAZAKI TAKAO , ISHIHARA HAYATO , NISHIKAWA NORIMITSU
IPC分类号： H03M1/10 , H03M1/18 , H03M1/36
摘要： PURPOSE:To simultaneously perform the highly accurate offset adjustment and gain adjustment of an analog/digital converter by making the dynamic range of analog signals to be inputted and the dynamic range of an analog/ digital conversion circuit be coincident. CONSTITUTION:The dynamic range of input analog signals and the dynamic range of this A/D converter M are made coincident. In other words, the entire bits of A/D converted digital signals are turned to a first logical value when the level of the input analog signals is a maximum value and the entire bits of the A/D converted digital signals are turned to a second logical value when the level of the input analog signals is a minimum value. That is, inputting the analog signals Ain to the A/D conversion circuit M after desired first voltage V1 and second voltage V2 are adjusted means that the dynamic range of the input analog signals Ain and the dynamic range of the A/D conversion circuit M are made coincident and highly accurate A/D conversion is made possible.

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