专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS59218693A Address converting system 失效
标题翻译：地址转换系统
公开(公告)号：JPS59218693A
公开(公告)日：1984-12-08
申请号：JP9375483
申请日：1983-05-27
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp
发明人： TAJIRI KAZUO , INOUE MASANOBU , SAWAMOTO HIDEO , UEDA KOUICHI
IPC分类号： G06F12/10 , G11C9/06 , G06F13/00
CPC分类号： G06F12/10
摘要： PURPOSE:To increase the independent characteristics of a virtual address space for address conversion of an information processor applying a multiplex virtual address system by invalidating the effect of a bit (c) to a specific virtual address space VS and allotting different programs or data to the virtual addresses which are used with the allotment of common programs or data for other plural spaces VS. CONSTITUTION:When VS1 or VS2 is switched to VS3, a control program sets 3 as VSID11 of a register 9, the head address of an address conversion table corresponding to the VS3 as ATO10 and 1 to an I bit 12 since the VS3 has no program nor data 4 common to the VS1 or VS2. As a result, the output of an AND gate 22 is set at 0 regardless of (c) bit 17. Then a TLB entry which has VS15 coincident with VA18 and VSID14 coincident with the VSID11 of the TR9 (3 in this case) can be used for address conversion of the VA18. In other words, only (3,a,delta,c=0) can be used for the conversion of a virtual address (a). Then (1,a,alpha,c=1) or (2,a,alpha,c=1) is never used by mistake even though they remain within a TLB.
摘要翻译：目的：通过使比特（c）对特定虚拟地址空间VS的影响无效并将不同的程序或数据分配给该虚拟地址空间VS来增加用于应用多路复用虚拟地址系统的信息处理器的地址转换的虚拟地址空间的独立特性虚拟地址与其他多个空间VS的公用程序或数据的分配一起使用。构成：当VS1或VS2切换到VS3时，控制程序将3设为寄存器9的VSID11，将VS3作为ATO10和1对应的地址转换表的头地址设置为I位12，因为VS3没有程序也不是对VS1或VS2通用的数据4。结果，与（c）位17相比，AND门22的输出被设置为0.然后，与TR9（在这种情况下为3）的VSID11一致的具有VS15的VS15一致的TLB条目可以是用于VA18的地址转换。换句话说，只有（3，a，delta，c = 0）可以用于虚拟地址（a）的转换。那么即使它们保留在TLB内，也不会错误地使用（1，a，α，c = 1）或（2，a，α，c = 1）。

2. 发明专利

JPS59154553A Debugging interruption system 失效
标题翻译：调试中断系统
公开(公告)号：JPS59154553A
公开(公告)日：1984-09-03
申请号：JP2915983
申请日：1983-02-23
申请人： Nippon Telegr & Teleph Corp
发明人： TAJIRI KAZUO , YAMAGUCHI KAZUYUKI
IPC分类号： G06F11/28 , G06F9/48 , G06F11/36
CPC分类号： G06F11/36
摘要： PURPOSE:To add the contents of a specific field to the address of an instruction and thus obtain an instruction address to be stored in a memory on the generation of an interruption, by causing a debugging interruption by an instruction having a specific instruction code. CONSTITUTION:The address of an instruction to be executed next in the processing of the debugging interruption is represented as SCC, the program state word in an information processor is represented as PSW, and an instruction for the debugging interruption is represented as a DI instruction. If the PSW indicates a debugging state when the DI instruction 9 is present in an address specified by the SCC of the PSW and the information processor decodes an F field to identify the DI instruction, the information processor updates the SCC in the PSW by the value obtained by adding the value in the R1 field 11 of the DI instruction 9 to the SCC, generating a debugging interruption signal. Further, the contents of the PSW including the SCC after update are stored in a specific memory address as an old PSW.
摘要翻译：目的：将特定字段的内容添加到指令的地址，从而通过具有特定指令代码的指令进行调试中断，从而获得存储在存储器中的生成中断的指令地址。构成：在调试中断处理中接下来要执行的指令的地址表示为SCC，信息处理器中的程序状态字表示为PSW，调试中断指令表示为DI指令。如果在由PSW的SCC指定的地址中存在DI指令9时，PSW表示调试状态，信息处理器对F字段进行解码以识别DI指令，则信息处理器将PSW中的SCC更新为值通过将DI指令9的R1字段11中的值添加到SCC获得，产生调试中断信号。此外，包括更新后的SCC的PSW的内容被存储在作为旧PSW的特定存储器地址中。

3. 发明专利

JPS60229153A CONSTITUTION CONTROL SYSTEM OF COMPUTER SYSTEM 失效
公开(公告)号：JPS60229153A
公开(公告)日：1985-11-14
申请号：JP8438784
申请日：1984-04-26
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： TAJIRI KAZUO , INOUE MASANOBU , SUMIMOTO TSUTOMU , IKEDA HITOSHI
IPC分类号： G06F12/16 , G06F12/06
摘要： PURPOSE:To prevent program control from complexity due to the difference in memory constitution by dividing plural memory devices into plural sets and previously preparing plural modes for the combination of address numbers to be assigned to respective constitutional units. CONSTITUTION:Four constitutional units consisting of machine numbers 0-3 are prepared in a memory device MEM5 and four constitutional units consisting of machine numbers 8-11 are prepared in a memory device MEM6. If a single computer system is to be constituted by all devices shown in a Fig., a service processor SVP9 connects memory devices MCUs 7, 8, CPUs 1, 2, data transfer devices DCHs 3, 4, and the MEMs 5, 6 respectively to initialize the system. To obtain a continuous real address space, address numbers 0-7 are assigned to eight machine Nos. in the MEMs 5, 6. Therefore, the SVP9 selects one mode out of four address number assigning modes to assign the address number. If independent processing is started due to a trouble or the like, it is necessary to stop the use of respective devices, but the specification of an address number may be stopped in the MEM6.

4. 发明专利

JPS5794973A CONTROL SYSTEM FOR BUFFER MEMORY 失效
公开(公告)号：JPS5794973A
公开(公告)日：1982-06-12
申请号：JP17124680
申请日：1980-12-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HATSUTORI AKIRA , TAKAHASHI MASANORI , HIGASHIDA MASANOBU , TAJIRI KAZUO
IPC分类号： G06F13/12 , G06F12/08 , G06F12/12
摘要： PURPOSE:To prevent the processing speed of a CPU from decreasing by preventing a change in the replacement priority level of a block which contains a readout request address from a channel device when the block is stored in a buffer memory. CONSTITUTION:When an access readout request from a channel 4 to a buffer memory 2 is detected at a memory port 28 for channels, an update logical circuit 5 is inhibited through a signal line 29 from operating. Therefore, if an access request block from the channel is in a buffer, the expelling priority level of the block is not changed. When it is not in the buffer, the block is substituted for the oldest block, but since the update logic circuit 5 is not in operation at this time, the channel uses only the way position where the oldest block was resident, so that a CPU is not interrupted.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式