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1. 发明专利

JPH06119368A SIMULTANEOUS EQUATIONS ANALYZING COMPUTER BY RELAXATION METHOD 失效
公开(公告)号：JPH06119368A
公开(公告)日：1994-04-28
申请号：JP24809991
申请日：1991-09-26
申请人： HITACHI LTD , TANAKA MAMORU
发明人： SHIMIZU NAOHIKO , TANAKA MAMORU
IPC分类号： G06F15/16 , G06F15/173 , G06F17/12 , G06F15/324
摘要： PURPOSE:To attain high speed and high performance by calculating the different variable of simultaneous equations by connecting plural calculating elements in the form of a ring, and transferring its own calculated value to the neighboring calculating element in this process. CONSTITUTION:The calculating elements PE1 to PEN are connected in the form of the ring by the data line of a single direction so as to communicate with each other. This ring is provided with a gateway processor GE to communicate with a host CPU, and it executes the setting-up of the calculating element, the sending of a command and the judgement of convergence. In a specified step in the calculation of a relaxation method, each calculating element PE1 to PEN analyzes different linear simultaneous equations respectively, and transfers an analyzed result to the neighboring calculating element. In the next step, the calculating element having received this transfer executes the analysis of a succeeding step by using the received analyzed result. Accordingly, high- speed relaxation method calculation can be executed, and besides, each claculating element need only have small traffic, and the analysis calculation of the high performance can be realyzed.

2. 发明专利

JPH04184557A REQUEST CONTENTION GENERATING SYSTEM 失效
公开(公告)号：JPH04184557A
公开(公告)日：1992-07-01
申请号：JP31515290
申请日：1990-11-20
申请人： HITACHI LTD
发明人： TANIGUCHI TOSHIHISA , OTANI ISAO , SHIMIZU NAOHIKO , KISHI MAKOTO
IPC分类号： G06F15/16 , G06F11/22 , G06F15/177
摘要： PURPOSE:To arbitrarily and surely generate request contention by generating a pseudo request by triggering a request from a certain processor. CONSTITUTION:When logic verification is made, a select circuit 13 is controlled to select a request buffer 12. When the buffer 12 is selected,a request issued by an instruction processor is accepted not only by a request buffer 10, but also by another request buffer 12. Accordingly, such an environment that requests are generated from instruction processors 1 and 2 in a contentious state is realized when viewed from a priority section 3. In addition, a similar contentious environment can also be realized when viewed from the section 3 even in a single processor constitution which does not use the processor 2, but the processor 1 only. Therefore, a request contentious state can be arbitrarily generated between processors and request contention tests can be performed intentionally.

3. 发明专利

JPH01171021A SORTING PROCESSOR 失效
公开(公告)号：JPH01171021A
公开(公告)日：1989-07-06
申请号：JP33132987
申请日：1987-12-26
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SHIMIZU NAOHIKO , YADA KIYOSHI , GENDAI YUUJI , SATO TETSUJI , TAKEDA HIDEAKI , FUKUOKA HIDEKI
IPC分类号： G06F7/24
摘要： PURPOSE:To speed up the classifying/counting processing of a record by executing a sorting processing and simultaneously, executing the detection and counting processing of a superimposed record. CONSTITUTION:A sorting processing means 11 compares mutually an input record, rearranges it based on the size of a record and outputs the record in the sequence of ascending or in the sequence of descending. By the mutual comparison of the record, a superimposing detecting means 13 detects during the sorting processing that two records or above the coincident, and decides superimposing. A counting means 14 counts the number of records which are decided to be the superimposing by the superimposing detecting means 13. Thus, the detection of the superimposed record and the counting of the superimposed record are simultaneously executed during the sorting processing. Thus, the classification and counting processing of the record can be executed at a high speed.

4. 发明专利

JPH04127240A INTERRUPTION CONTROL METHOD AND INSTRUCTION PROCESSOR 失效
公开(公告)号：JPH04127240A
公开(公告)日：1992-04-28
申请号：JP24844190
申请日：1990-09-18
申请人： HITACHI LTD
发明人： SHIMIZU NAOHIKO , YAMAGATA MAKOTO , SHIBATA MASABUMI
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To attain the parallel operations with high performance in a simple constitution by storing the information that specifies an instruction carried out in advance in a period covering the production of an interruption through the saving of a program state word into this word. CONSTITUTION:A program state word PSW is provided with an execution instruction map XM and a branch execution flag B. At the same time, a branching destination address word TAW is newly added. Then the information specifying an instruction that is carried out in a period covering the production of an instruction through the saving of the PSW is stored into the PSW which is saved when the interruption of an instruction processor is produced. Therefore the PSW shows an instruction that produced an interruption and also the instruction already carried out at production of the interruption is shown in a bit map. Thus it is not required to sequentially and serially produce the instructions when an instruction having the possibility for production of an interruption is carried out. Thus the executing performance is improved. In such a simple constitution, an instruction processor of high performance can be obtained.

5. 发明专利

JPH0312736A METHOD AND DEVICE FOR PROCESSING MERGE 失效
公开(公告)号：JPH0312736A
公开(公告)日：1991-01-21
申请号：JP14859189
申请日：1989-06-12
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SHIMIZU NAOHIKO , YADA KIYOSHI , GENDAI YUUJI , SATO TETSUJI , TAKEDA HIDEAKI , FUKUOKA HIDEKI
IPC分类号： G06F7/32
摘要： PURPOSE:To facilitate a merge process even if the number of records is unknown in a record train by adding a final record identifier and a train identifier to each record of a sorted record train, discriminating the train to be selected next with the train identifier and discriminating the end of a record train with a record identifier respectively. CONSTITUTION:An input circuit 1 reads the records out of a memory 21, and a sorting circuit 2 sorts the maximum K units of records. These sorted records are outputted from an output circuit 5 via a discriminating circuit 3. Each record includes a sort data KEY, a record identifier SID, and a final record identifier EOS. The SIDs included in each i-th record string are all equal to (i). The final record of a train has its EOS equal to 1 and other records have the EOSs equal to 0 respectively. A discriminating circuit 3 discriminates the outputs of the circuit 2 into three types. An output circuit 5 collects the sorting data received from the circuit 3, a new data train identifier 9 received from a control circuit 7, and a final record identifier 17 to produce an output record. Then the circuit 7 controls an entire merge process. In such a constitution, the merge process is facilitated even if the number of records is unknown in a record train.

6. 发明专利

JPH0228878A DATA BASE PROCESSOR 失效
公开(公告)号：JPH0228878A
公开(公告)日：1990-01-30
申请号：JP18128788
申请日：1988-07-19
申请人： HITACHI LTD
发明人： YADA KIYOSHI , SHIMIZU NAOHIKO
IPC分类号： G06F17/30
摘要： PURPOSE:To successively supply data from a search processor to a sort processor by operating the search processor and the soft processor in an interlocking operation mode and executing a data base processing. CONSTITUTION:A search processor 3 is connected with a CPU 1 through an I/O interface 2 and retrieves the data base stored in a disk device 4. A sort processor 5 sorts the data base. The CPU 1 executes the processing in an independent operation mode to operate the search processor 3 and the sort processor 5 independently or in the interlocking operation mode to operate the search processor 3 and the sort processor interlockingly.

7. 发明专利

JPS63255742A DATA PROCESSOR 失效
公开(公告)号：JPS63255742A
公开(公告)日：1988-10-24
申请号：JP8982887
申请日：1987-04-14
申请人： HITACHI LTD
发明人： YADA KIYOSHI , SHIMIZU NAOHIKO
IPC分类号： G06F11/14 , G06F11/22
摘要： PURPOSE:To automatically continue a fault test without requiring manual operations by providing an FF which automatically resets a CPU stopped with a fault and generates a restart interruption thereafter. CONSTITUTION:A CPU 1 instructs the execution of a test program 4 and starts the fault test. A program which generates the fault is incorporated in this test program, and the fault is generated by the instruction of the program. The CPU 1 detects this fault to interrupt the instruction processing and informs an SVP 2 of the fault. The SVP 2 analyzes the fault to check whether the processing of the CPU 1 can be executed again or not. The restart processing or the stop processing of the CPU 1 is performed. After the execution of the stop processing of the CPU 1, the CPU 1 is reset to generate the restart interruption when an RCP FF 3 is set.

8. 发明专利

JPS63201828A INFORMATION PROCESSOR 失效
公开(公告)号：JPS63201828A
公开(公告)日：1988-08-19
申请号：JP3322587
申请日：1987-02-18
申请人： HITACHI LTD
发明人： YAMAGATA MAKOTO , SHIMIZU NAOHIKO
IPC分类号： G06F9/24 , G06F9/22 , G06F12/06
摘要： PURPOSE:To most suitably allocate microprograms on control storages different in operation speed by loading microprograms to the high-speed control storage and the low-speed control storage in accordance with frequency is execution. CONSTITUTION:The frequency in execution of instructions read into an instruction register 2 is counted at intervals of a certain time and the counted result is stored in a local storage 5. A service processor 9 edits contents of the storage 5 and records the result on a magnetic disk 10. At the next time of microprogram loading, the processor 9 determines whether the microcode stored on the disk 10 should be stored in a high-speed control storage 6 or a low-speed control storage 7 based on the frequency in execution of the microprogram stored on the disk 10 and stores the microcode in the storage 6 or 7. Thus, microprograms are most suitably allocated on control storages with a relatively small amount of hardware.

9. 发明专利

JPH03231387A OPTICAL STORAGE DEVICE 失效
公开(公告)号：JPH03231387A
公开(公告)日：1991-10-15
申请号：JP2601890
申请日：1990-02-07
申请人： HITACHI LTD
发明人： SHIMIZU NAOHIKO
IPC分类号： G06K7/015
摘要： PURPOSE:To correct the mechanical accuracy of a card and a sensor and to reduce the power consumption by editing outputs of plural sensors by a result of detection of a position detecting means. CONSTITUTION:In a first and a second pilot track detecting circuits 221, 222, a pilot pulse is counted and by a position information detector for detecting an absolute position on each track, a pilot track position of a card is confirmed. A data input control circuit 223 converts a read-out position correction to a multiplexer selecting signal and inputs it to a data track editing circuit 224. Also, a read-out time correction is performed to a data input of a FIFO buffer 225.

10. 发明专利

JPH01177125A SORT PROCESSOR 失效
公开(公告)号：JPH01177125A
公开(公告)日：1989-07-13
申请号：JP161688
申请日：1988-01-07
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： GENDAI YUUJI , SATO TETSUJI , YADA KIYOSHI , SHIMIZU NAOHIKO , TAKEDA HIDEAKI , HAYAMIZU HARUO
IPC分类号： G06F7/24 , G06F7/36
摘要： PURPOSE:To detect a sorting error with no delay of time from occurrence of said error in a merge operating process which is repetitively carried out by checking the sequence of records received from a sorting circuit. CONSTITUTION:A sorting circuit 11 consists of a 1-dimensional array of comparison/transfer units 21 containing a memory 22 storing two records, a comparator 24 for records, etc., respectively. The circuit 11 entirely stores (k) pieces of records (k: an integer larger than 1) and performs the comparison/ transfer processing for output of the maximum or minimum record out of those stored ones. In this case, a fact that the sequence of arrangement of the records received from the circuit 11 has no error is confirmed synchronously with the output of records. Thus it is possible to detect a sorting error with no delay of time from occurrence of said error in a merge operating process which is repetitively carried out.

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