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1. 发明专利

JPS60234297A DYNAMIC RAM 失效
公开(公告)号：JPS60234297A
公开(公告)日：1985-11-20
申请号：JP8940784
申请日：1984-05-07
申请人： HITACHI LTD
发明人： SATOU KATSUYUKI
IPC分类号： G11C11/401 , G11C11/34 , G11C11/4099
摘要： PURPOSE:To increase the reading speed of a dynamic RAM by short-circuiting a data line connected with a dummy cell to increase the stray capacity and controlling a reference voltage potential. CONSTITUTION:A memory cell MC connected to a data line DL, etc. via a word line WL1 and a line WL1', etc. is selected together with a cell MC connected to a line DL' which is complementary to the line DL and a dummy cell DC corresponding to the CM. In this case, the FETQ1 and Q2 are turned off and on respectively and the stray capacity of the DL' is double as much as that of the DL. Thus the capacity ratio of the cell DC to the DL' goes to 1/2 ratio of the cell MC to the DL. Therefore, the capacity ratio of the MC to the DL is equal to that of a half-size DC to the DL'. The reference voltage of the DL' is set at the middle level between high and low levels of voltage applied to the MC from the DL. Thus the storage contents of a high level can be extracted at a high speed to a low level of the reference voltage in a read mode. As a result, the reading speed is increased with a dynamic RAM.

2. 发明专利

JPS5933696A Dynamic misram 失效
标题翻译：动态MISRAM
公开(公告)号：JPS5933696A
公开(公告)日：1984-02-23
申请号：JP14113182
申请日：1982-08-16
申请人： Hitachi Ltd
发明人： SATOU KATSUYUKI
IPC分类号： G11C11/407 , G11C11/34
CPC分类号： G11C11/34
摘要： PURPOSE:To obtain a high-speed dynamic MISRAM with a simple constitution, by supplying electric power to a selected word line from the furthest side of the word line via a word line amplifier. CONSTITUTION:An FETQ5 of a word line amplifier W-AMP of the selected word line VW is turned on by a clock phi1, and therefore FETQ1 and Q2 are turned on with an FETQ4 turned on. Then the clock phi1 is turned on, and the electric power is supplied also from the furthest side of the line VW via a bootstrap capacity CB1. In the same way, the electric power is supplied to a dummy word line VWO. As a result, the writing/reading is carried out with no delay to an RAM memory cell at the furthest side of the word line with a simple constitution and regardless of the resistance of the word line. This ensures a high- speed operation of a dynamic MISRAM.
摘要翻译：目的：通过简单的结构获得高速动态MISRAM，通过字线放大器，从字线最远侧的选定字线提供电力。构成：所选字线VW的字线放大器W-AMP的FETQ5由时钟phi1导通，因此FETQ1和Q2导通，FETQ4导通。然后，时钟phi1被接通，并且还通过自举容量CB1从线路VW的最远侧提供电力。以相同的方式，将电力提供给虚拟字线VWO。结果，以简单的结构，无论字线的电阻如何，对字线的最远侧的RAM存储单元没有延迟地进行写入/读取。这确保了动态MISRAM的高速运行。

3. 发明专利

JPS58166827A DELAY CIRCUIT 失效
公开(公告)号：JPS58166827A
公开(公告)日：1983-10-03
申请号：JP4888782
申请日：1982-03-29
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SATOU KATSUYUKI , KOYAMA YOSHIHISA
IPC分类号： H03K5/13
摘要： PURPOSE:To extend the delay time for a delay circuit having a large time constant, by avoiding the effect of variation of the power supply voltage to the delay time although an input signal has dependance on the power supply voltage. CONSTITUTION:Load MOSFETs Q5 and Q6 are connected in series between MOSFETs Q2 and Q4 which are driven by two signals phi1 and phip' having almost opposite phases to each other. Then the gate voltage which is a little higher than the threshold voltage is supplied to a driving MOSFETQd. This process can eliminate the dependance on the power supply voltage for the delay time. Then the stable delay time is obtained even at the side of high voltage.

4. 发明专利

JPS5850019A SUBSTRATE BIAS VOLTAGE GENERATING CIRCUIT 失效
公开(公告)号：JPS5850019A
公开(公告)日：1983-03-24
申请号：JP14789581
申请日：1981-09-21
申请人： HITACHI LTD
发明人： SATOU KATSUYUKI
IPC分类号： G05F3/24 , G05F3/20 , G11C11/407 , H01L21/822 , H01L27/04
摘要： PURPOSE:To generate a substrate bias voltage havong a large absolute value, by supplying a pulse signal, which is generated in an output buffer circuit of an oscillating circuit, and a signal, which is generated in a bootstrap circuit, to a rectifying circuit. CONSTITUTION:A pulse signal NA, which is generated in an output buffer circuit, PP, out of signals of an oscillating circuit OSC is changed periodically between reference potential and a power source voltage VCC, and a pulse signal NB generated in a bootstrap circuit BP is changed synchronously with the signal NA. When the level of the signal NA is changed from the high level to the low level, a voltage NC of the other electrode of a capacitor C2 is changed in the negative direction by voltage components corresponding to a stored charge quantity, and an FETQ11 is turned on, and a parastic capacity CS between a circuit reference potential point and a substrate SUB is charged. As the result, a substrate bias voltage -VBE is lowered to a voltage -(VCC-Vth11) when the threshold voltage of the FETQ11 is denoted as Vth11.

5. 发明专利

JPS6122492A Dynamic ram 失效
标题翻译：动态RAM
公开(公告)号：JPS6122492A
公开(公告)日：1986-01-31
申请号：JP14233284
申请日：1984-07-11
申请人： Hitachi Ltd
发明人： ONO KUNIO , YANAGISAWA KAZUMASA , SATOU KATSUYUKI
IPC分类号： G11C11/407 , G11C11/34 , G11C11/409
摘要： PURPOSE: To improve an action margin and to speed up an action by regulating column selection timing with the aid of a signal fromed by monitoring the action state of a sensor amplifier.
CONSTITUTION: The action voltage Sn of a sensor amplifier SA is monitored by an inverter IV2 the farthest from power switch N-channel MOSFETs Q10 and Q11 and P-channel MOSFETs Q12 and Q13. When the fact is detected that the necessary and sufficient voltage for an amplifying action is supplied, and a voltage Sm comes to about a grounding potential, a timing signal ϕ
sm outputted by the inverter IV2 goes to "H", and an AND gate G is opened, whereby a selection signal ϕy is supplied to a column decoder C-DCR. Consequently, the column selection timing can be set at the optimum timing irrespective of the dispersion of an element characteristic and the fluctuation of a power source, and the useless time margin is made unnecessary. As a result, an action margin can be improved and an action can be sped up.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过监控传感器放大器的动作状态，借助于信号调节列选择时间，提高动作余量并加快动作速度。构成：传感器放大器SA的动作电压Sn由与功率开关N沟道MOSFET Q10和Q11以及P沟道MOSFET Q12和Q13最远的反相器IV2监视。当检测到提供用于放大动作的必要和足够的电压并且电压Sm接近接地电位的事实时，由反相器IV2输出的定时信号phism变为“H”，并且“与”门 G被打开，由此选择信号phiy被提供给列解码器C-DCR。因此，无论元件特性的偏差和电源的波动如何，都可以将列选择定时设定为最佳定时，并且不需要无用的时间余量。结果，可以提高动作余量，并且可以加快动作。

6. 发明专利

JPS60211524A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS60211524A
公开(公告)日：1985-10-23
申请号：JP6769184
申请日：1984-04-06
申请人： Hitachi Ltd
发明人： SATOU KATSUYUKI
IPC分类号： H02J1/00 , G06F1/00 , G06F1/26 , G11C11/34 , G11C11/413
摘要： PURPOSE: To obtain a semiconductor integrated circuit device having backup identification function by providing a complementary MOS inverter circuit comprising a P-channel MOSFET and an N-channel MOSFET.
CONSTITUTION: The complementary CMOS inverter circuit activated by the same power supply voltage as that for an internal circuit (static RAM, SRAM) and comprising the P-channel MOSFETQ3 and the N-channel MOSFETQ4 is provided. When a system power supply voltage V
cc is applied, since the level of the input to the CMOS inverter circuit is brought into a high level via a Q1, its output signal goes to a low level. Thus, the output signal of an OR gate G1 is brought into a level according to the level of a chip selection signal CS. When the power supply is interrupted, the output signal of the CMOS inverter circuit goes to a high level, the chip selection signal is brought forcibly into the chip non-selection state of high level to attain backup.
COPYRIGHT: (C)1985,JPO&Japio
摘要翻译：目的：通过提供包括P沟道MOSFET和N沟道MOSFET的互补MOS反相器电路，获得具有备份识别功能的半导体集成电路器件。构成：提供与内部电路（静态RAM，SRAM）相同的电源电压激活并且包括P沟道MOSFETQ3和N沟道MOSFETQ4的互补CMOS反相器电路。当施加系统电源电压Vcc时，由于通过Q1使CMOS反相器电路的输入电平达到高电平，所以其输出信号变为低电平。因此，或门G1的输出信号根据芯片选择信号CS的电平进入一个电平。当电源中断时，CMOS反相器电路的输出信号变为高电平，芯片选择信号强制进入高电平的芯片非选择状态，以备备。

7. 发明专利

JPS58159124A TIMING GENERATOR 失效
公开(公告)号：JPS58159124A
公开(公告)日：1983-09-21
申请号：JP4079682
申请日：1982-03-17
申请人： HITACHI LTD
发明人： SATOU KATSUYUKI
IPC分类号： G06F1/04
摘要： PURPOSE:To obtain a circuit having small dependance on the power supply voltage, by providing a bootstrap circuit between a circuit which delays an input signal and a timing generating circuit and raising the gate potential of an MOSFET up to a level higher than the power supply voltage. CONSTITUTION:Input signals phiin and -phi are applied to the gates of MOSFETs Q1 and Q2. When the signals -phi and phiin are set L and H, respectively, the MOSFETs Q1 and Q2 are turned off and on, respectively. At the same time, MOSFETs Q3 and Q4 are turned off and on. Then the potential at a point (a) is delayed and lowered by a resistance Rd, and at the same time the drain side potential of a Qc has a rise of its level later than the signal in and set at a level H to be turned on. Thus the bootstrap capacity Cb is charged continuously until an MOSFETQ5 is turned off by a drop of potential at the point (a). Thus the potential of a node A rises up toward Vcc to raise the gate potential of an MOSFETQ6 up to a level higher than Vcc. As a result, the rise of the node A is not delayed so much although the Vcc is dropped. This process can reduce the dependance on the power supply voltage for the delay time of a whole device.

8. 发明专利

JPS59185090A Dynamic ram 失效
标题翻译：动态RAM
公开(公告)号：JPS59185090A
公开(公告)日：1984-10-20
申请号：JP5508583
申请日：1983-04-01
申请人： Hitachi Ltd
发明人： SATOU KATSUYUKI
IPC分类号： G11C11/407 , G11C11/34 , G11C11/401 , G11C11/409
CPC分类号： G11C11/34
摘要： PURPOSE:To attain highly accurate control by utilizing a dummy word line so as to simulate the level increase at the remotest end of the word line thereby discriminating an optimum level so as to start a word line bootstrap circuit. CONSTITUTION:External address signals AX0-AXn are fetched to an address buffer ADB in synchronizing with a timing signal phiar formed by a row address strobe signal RAS and fed to a row decoder R-DCR and also the selecting operation of the prescribed word line and dummy word line is attained by using a word line selection timing signal phix. This timing signal phix is inputted to the boostrap circuit phix-B so as to boost the potential of the selected word line WL to a voltage over power supply voltage Vcc. Further, external address signals AY0-AYn are fetched to an address buffer ADB in synchronizing with a timing signal phiac formed by a column address strobe signal CAS, fed to a column decoder C-DCR and the data line is selected by a data line selection timing signal phiy.
摘要翻译：目的：通过利用虚拟字线来实现高精度的控制，以便模拟字线最远端的电平增加，从而识别最佳电平以便启动字线自举电路。构成：外部地址信号AX0-AXn与由行地址选通信号RAS形成的定时信号phi同步地被提取到地址缓冲器ADB，并被馈送到行解码器R-DCR，并且还指定规定字线的选择操作，通过使用字线选择定时信号phix来获得虚拟字线。该定时信号phix被输入到脉冲电路phix-B，以便将所选字线WL的电位升高到电源电压Vcc上的电压。此外，外部地址信号AY0-AYn与由列地址选通信号CAS形成的定时信号phiac同步地被提取到地址缓冲器ADB，该定时信号由输入到列解码器C-DCR的列地址选通信号CAS，并且数据线被数据线选择定时信号phiy

9. 发明专利

JPS5924495A Bootstrap circuit 失效
标题翻译： BOOTSTRAP电路
公开(公告)号：JPS5924495A
公开(公告)日：1984-02-08
申请号：JP13372282
申请日：1982-08-02
申请人： Hitachi Ltd
发明人： SATOU TAKASHI , SATOU KATSUYUKI
IPC分类号： G11C11/407 , G11C7/00 , G11C11/34 , H03K17/06
CPC分类号： G11C11/34
摘要： PURPOSE:To improve the efficiency of boosting, by installing an element which is controlled by a signal of a phase reverse to a delay pulse around an electrode at the delay pulse side and enlarging the pulse amplitude of another electrode of boosting capacity. CONSTITUTION:When the output pulse phiX of a pulse generating circuit phiX-G rises to a high level VCC, charging up is performed on a bootstrap capacity CB and a parasitic capacity Clb. Therefore, the node N of the electrode at the diffused layer side of the bootstrap capacity CB, which is the connecting point of both, is brought up to an intermediate voltage V1 in accordance with the capacity ratio of both capacities CB and Cb. When the delay signal phix' of a delay circuit D becomes a high level VCC, a voltage held by the bootstrap capacity CB is added to this voltage VCC and the selection level of a word line of a dynamic type RAM is formed at a high voltage. Therefore, delivery and reception of a writing/reading-out level against a memory cell can be performed without any level loss caused by the threshold voltage of the switching MOS FET of the memory cell.
摘要翻译：目的：通过在延迟脉冲侧安装由与电极周围的延迟脉冲相反的相位信号控制的元件，并且增大另一个升压电极的脉冲幅度来提高升压效率。构成：当脉冲发生电路phiX-G的输出脉冲phiX上升到高电平VCC时，在自举电容CB和寄生电容Clb上进行充电。因此，作为两者的连接点的自举电容CB的扩散层侧的电极的节点N根据容量CB和Cb的容量比而升高到中间电压V1。当延迟电路D的延迟信号phix'变为高电平VCC时，由自举电容CB保持的电压加到该电压VCC上，并且动态类型RAM的字线的选择电平以高电压形成。因此，可以执行对存储单元的写入/读出电平的传送和接收，而不会由存储单元的开关MOS FET的阈值电压引起的任何电平损耗。

10. 发明专利

JPS58156226A DELAY CIRCUIT 失效
公开(公告)号：JPS58156226A
公开(公告)日：1983-09-17
申请号：JP3802382
申请日：1982-03-12
申请人： HITACHI LTD
发明人： SATOU KATSUYUKI
IPC分类号： H03K5/00 , H03K5/13
摘要： PURPOSE:To reduce the dependence of the delay time on a power supply, by supplying the gate voltage of a signal delaying MOSFET from the output voltage of a bootstrap circuit of an inverter of the front stage. CONSTITUTION:The output voltage of an inverter 1a is increased up to the power supply voltage VCC by a bootstrap circuit 3. At the same time, the output at a node A, i.e., the output voltage of a delay circuit 2 also reaches the voltage VCC since the gate voltage of an MOSFETQ5 is boosted by the circuit 3. When the voltage at the node A reaches the VCC, the relative degree of fluctuation of the voltage at the node A which is due to variations of the power supply voltage is reduced in comparison with a case where the level of voltage is low. Thus the delay time of the circuit 2 is not easily affected by variations of the power supply voltage.

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