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1. 发明专利

JP2518855B2 失效
公开(公告)号：JP2518855B2
公开(公告)日：1996-07-31
申请号：JP16232087
申请日：1987-07-01
申请人： HITACHI LTD
发明人： KIMURA MASATOSHI , SATONAKA KOICHIRO , KODA TOYOMASA , OKABE TAKEAKI , SAKAMOTO MITSUZO
IPC分类号： H01L29/78 , H01L21/76 , H01L21/8249 , H01L27/06 , H01L27/088

2. 发明专利

JPH0469431B2 失效
公开(公告)号：JPH0469431B2
公开(公告)日：1992-11-06
申请号：JP19464484
申请日：1984-09-19
申请人： HITACHI LTD
发明人： YAMADA TOMIO , SATONAKA KOICHIRO , HOSHI AKIRO
IPC分类号： H01L23/50 , H01L21/48 , H05K3/34

3. 发明专利

JPS6352470B2 失效
公开(公告)号：JPS6352470B2
公开(公告)日：1988-10-19
申请号：JP14890279
申请日：1979-11-19
申请人： HITACHI LTD
发明人： SATONAKA KOICHIRO , SHINDO YOSHIMI
IPC分类号： H01L27/04 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L27/02

4. 发明专利

JPS5846853B2 JPS5846853B2 - 失效
公开(公告)号：JPS5846853B2
公开(公告)日：1983-10-19
申请号：JP10218975
申请日：1975-08-25
申请人： Hitachi Ltd
发明人： SATONAKA KOICHIRO
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522
CPC分类号： H01L24/02 , H01L2924/01014 , H01L2924/14 , H01L2924/00

5. 发明专利

JP2533500B2 失效
公开(公告)号：JP2533500B2
公开(公告)日：1996-09-11
申请号：JP22352186
申请日：1986-09-24
申请人： HITACHI LTD
发明人： KIMURA MASATOSHI , OKABE TAKEAKI , SAKAMOTO MITSUZO , KODA TOYOMASA , SATONAKA KOICHIRO
IPC分类号： H01L21/8249 , H01L21/76 , H01L21/8222 , H01L21/8234 , H01L21/8248 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/78

6. 发明专利

JPH0290541A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0290541A
公开(公告)日：1990-03-30
申请号：JP24113688
申请日：1988-09-28
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： KANAZAWA TAKAMITSU , SATONAKA KOICHIRO
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
摘要： PURPOSE:To enable easy positioning and alignment of connection parts and also highly accurate and small-sized packaging by a method wherein flat wiring terminals of a chip having larger dimensions and bumps of a chip having smaller dimensions are made to oppose to each other. CONSTITUTION:A first chip 1 is a chip, which is provided on the side of a substrate, and has comparatively large dimensions, a row of bumps 3 is provided along the peripheral edge part of the chip 1 and a row of pads 5 is provided along the inside of the row of bumps. A second chip is chip, which is provided on the side (over the first chip) opposite to the chip 1 in the case of assembly, and is formed as a chip having dimensions smaller by the width of the bump region of the chip 1 compared to the chip 1. A row of bumps 4 is provided at positions, where pads (wiring terminals) are normally provided, along the peripheral edge of the second chip. A carrier chip 16 consists of a flexible insulator, penetrated holes 17 are bores at prescribed intervals in the tape 16 and a plurality of Cu leads 6 are annexed encircling each hole 17. The side of the inner (inside) lead of each lead is provided facing each hole 17. The tape is positioned on the chip 1 and the bumps of the chip 1 and the leads are connected to one another.

7. 发明专利

JPH025539A RESIN-SEALED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH025539A
公开(公告)日：1990-01-10
申请号：JP15477788
申请日：1988-06-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAGUCHI KAZUYO , SATONAKA KOICHIRO
IPC分类号： H01L21/60 , H01L23/48
摘要： PURPOSE:To improve the humidity resistance of the title device by a method wherein metal layers for bonding use to improve bondability are each provided only on the bonded parts of bonding wires to each lead and a region, where the metal layers for bonding use do not exist, is provided on the peripheries of the bonded part of the leads. CONSTITUTION:Metal layers 7 for bonding use to improve bondability are each provided only on the bonded parts of bonding wires 5 to each of a tab 2A (or a lead 2B), a lead 2C and a lead 2D and a region where no layer 7 exists is provided on the peripheries of the respective bonded parts of the tab 2A and the leads 2C and 2D. As the bonded regions of each of the tab 2A and the leads 2C and 2D, whose adhesive properties to resin sealing parts 6 are high compared to the adhesive properties of the layers 7 to the parts 6, to the parts 6 are respectively provided on the peripheries of the bonded parts, the generation of a gap in these bonded regions is prevented and the intrusion of water content from the exterior can be reduced.

8. 发明专利

JPH01200659A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01200659A
公开(公告)日：1989-08-11
申请号：JP2472088
申请日：1988-02-04
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAGUCHI KAZUYO , SATONAKA KOICHIRO
IPC分类号： H01L23/28 , H01L23/50
摘要： PURPOSE:To stop the moisture creeping along the boundary between a resin seal package and a lead by forming a protruding part and a recessed part at the lead part situated inside the package. CONSTITUTION:In an IC having a resin seal type miniature square package, protruding parts 10a and recessed parts 10b are arranged alternately in the inner direction and outer direction at each lead 9 inside the package 14 and are formed collectively. When the protruding parts 10a and the recessed parts 10b are formed in the halfway part of the lead, a creeping route of the moisture from the outside of the package 14 to a wire and a pellet becomes long; accordingly, it is possible to prevent that the moisture which has crept reaches the wire and the pellet.

9. 发明专利

JPS6319844A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6319844A
公开(公告)日：1988-01-27
申请号：JP16373986
申请日：1986-07-14
申请人： HITACHI LTD
发明人： KIMURA MASATOSHI , OKABE TAKEAKI , YOSHIDA ISAO , SAKAMOTO MITSUZO , HOYA KAZUO , SATONAKA KOICHIRO , KODA TOYOMASA , OTAKA SHIGEO
IPC分类号： H01L27/08 , H01L21/331 , H01L21/76 , H01L21/8222 , H01L21/8234 , H01L21/8248 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/088 , H01L29/73 , H01L29/732 , H01L29/78
摘要： PURPOSE:To allow a transistor of high withstand voltage and large current and an element of low withstand voltage are made to coexist on the same chip under the optimum condition of structure by a method wherein a hole is formed by etching on the first conductive type semiconductor substrate, and the hole is buried by epitaxially growing the first epitaxial layer. CONSTITUTION:After an etching operation has been performed in the depth of about 15-20 mum on the part where the low withstand voltage element, namely, the part where a small signal circuit is formed, a P-type epitaxial layer 3 is buried by performing an epitaxial growing method. A deep hole is formed as above-mentioned, and the formation of a deep N type penetrated diffusion layer of high impurity density on the part of a power MOSFET is unnecessitated by burying the P-type epitaxial layer 3 to be used for isolation, and the drain electrode of a vertical type power MOSFET can be picked out directly from the N type substrate 1. Also, an N type buried layer 5 can be formed easily on a small signal circuit element part without giving an adverse effect on the power MOSFET part.

10. 发明专利

JPS5165585A Handotaishusekikairosochi 失效
公开(公告)号：JPS5165585A
公开(公告)日：1976-06-07
申请号：JP13841174
申请日：1974-12-04
申请人： Hitachi Ltd
发明人： SATONAKA KOICHIRO
IPC分类号： H01L21/3205 , H01L21/331 , H01L23/52 , H01L29/417 , H01L29/73 , H01L29/732
CPC分类号： H01L29/7322 , H01L29/41708

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