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1. 发明专利

JPS59139727A Cmos integrated circuit device 失效
标题翻译： CMOS集成电路设备
公开(公告)号：JPS59139727A
公开(公告)日：1984-08-10
申请号：JP1272483
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： YASUI NORIMASA , OGIUE KATSUMI , NISHIMURA KOUTAROU , ODAKA MASANORI , MIYAOKA SHIYUUICHI , TAKAHASHI OSAMU , YAMAMOTO AKIRA , SASAKI KATSUROU , YOU KANJI
IPC分类号： G11C11/407 , G11C11/409 , H03K19/0185
CPC分类号： H03K19/018514
摘要： PURPOSE:To give direct access to a CMOS static RAM through an ECL circuit and to facilitate production of a CMOS IC device by using an input level converting circuit which receives a signal of a level of emitter coupled logic ECL and converts it into a CMOS signal. CONSTITUTION:An input level converting circuit is provided to a CMOS IC device to receive a signal of ECL level and converts it into a signal of MOS level. Then an external address or a control signal is supplied to the base of an nMOS FETQ10 from a terminal ECLIN. A differential nMOSFETQ9 is connected to the FETQ10, and the reference voltage Vref for level dicision is applied to the base of the FETQ9. Then a constant current source containing an nMOSFETQ13 is connected to a common source. While pMOSFETs Q11 and Q12 which work as current mirror type active loads are connected to the drains of FETs Q9 and Q10 respectively. The voltage Vref is produced by a circuit consisting of partial pressure resistances R3 and R4, MOSFETs Q1-Q8, etc. Then direct access is given to a CMOS RAM through an ECL circuit.
摘要翻译：目的：通过ECL电路直接访问CMOS静态RAM，并通过使用输入电平转换电路来促进CMOS IC器件的生产，输入电平转换电路接收发射极耦合逻辑ECL的电平信号并将其转换为CMOS信号。构成：将输入电平转换电路提供给CMOS IC器件以接收ECL电平的信号并将其转换为MOS电平的信号。然后外部地址或控制信号从端子ECLIN提供给nMOS FETQ10的基极。差分nMOSFETQ9连接到FETQ10，并且用于电平切割的参考电压Vref被施加到FETQ9的基极。然后将包含nMOSFETQ13的恒流源连接到公共源。作为电流镜式有源负载工作的pMOSFET Q11和Q12分别连接到FET Q9和Q10的漏极。电压Vref由由部分压力电阻R3和R4，MOSFET Q1-Q8等组成的电路产生。然后通过ECL电路直接接入CMOS RAM。

2. 发明专利

JPS5924500A Redundancy circuit in semiconductor memory 失效
标题翻译：半导体存储器中的冗余电路
公开(公告)号：JPS5924500A
公开(公告)日：1984-02-08
申请号：JP13195682
申请日：1982-07-30
申请人： Hitachi Ltd
发明人： SASAKI KATSUROU
IPC分类号： G11C29/00 , G11C29/04
CPC分类号： G11C29/78
摘要： PURPOSE:To realize a redundancy circuit which is very simple in circuit configuration and small in occupying area, by automatically forming a signal which designates a preliminary memory group from a signal change-over circuit, and outputting the signal to a preliminary decoder. CONSTITUTION:An address signal, by which a preliminary memory column 3s is selected against a preliminary Y-decoder 6 when a prescribed address signal is inputted. The preliminary Y-decoder 6, for example, is set to a condition where its output attains a high level (selecting level) when the signal supplied from the signal change-over circuit 5 attains low level. By the output of the selecting level of the preliminary decoder 6, all the outputs of a normal Y-decoder 2 are inhibited and a column switch which selects a preliminary column 3s is turned on. That is to say, when the output of the preliminary Y-decoder attains a high level, any memory columns containing defective bits in a normal memory array 3 are not selected and the preliminary column 3s is selected instead of the former.
摘要翻译：目的：实现电路结构简单，占用面积小的冗余电路，通过自动形成从信号切换电路指定预备存储器组的信号，并将该信号输出到初步解码器。构成：当输入规定的地址信号时，通过该地址信号对预备的Y解码器6选择预备存储器列3s。例如，当从信号转换电路5提供的信号达到低电平时，初步Y解码器6被设置为其输出达到高电平（选择电平）的状态。通过初步解码器6的选择电平的输出，正常Y解码器2的所有输出被禁止，并且选择预备列3s的列开关被导通。也就是说，当初步Y解码器的输出达到高电平时，不选择包含正常存储器阵列3中的有缺陷位的任何存储器列，并且选择预备列3而不是前者。

3. 发明专利

JPS58194195A Output circuit 失效
公开(公告)号：JPS58194195A
公开(公告)日：1983-11-12
申请号：JP7533582
申请日：1982-05-07
申请人： Hitachi Ltd
发明人： YAMAMOTO AKIRA , MORIWAKI NOBUYUKI , SASAKI KATSUROU
IPC分类号： G11C11/419 , G11C7/10 , G11C11/409 , H03K5/00 , H03K19/017
CPC分类号： G11C7/10
摘要： PURPOSE:To decrease the level difference before and after the change in an output signal, to reduce the access time and to halve noise level generated at the signal change, by providing a circuit fixing an output terminal to an intermediate level between H and L, during the waiting time when an address signal is changed until the output level is confirmed. CONSTITUTION:A memory element of an address corresponding to address signals A0-An in a memory array 3 is selected with an address decoder 2 and the information stored in the element is read out. The read-out information (data signal) is amplified at a preamplifier 4 and outputted to an output terminal OUT from an output circuit 5 including an output buffer after the signal level is confirmed sufficiently. This output circuit is controlled with a control signal from a control circuit 6 and fixes a potential of the output terminal to an intermediate level between the high and the low level of the output signal, until the level of a data signal Pd outputted from the preamplifier 4 is confirmed after the address signal is changed. The delay time at the level change of the output signal is decreased, the high speed operation of the circuit is attained and the noise level induced with the change in the output signal is reduced.

4. 发明专利

JPS58166590A MOS STATIC RAM 失效
公开(公告)号：JPS58166590A
公开(公告)日：1983-10-01
申请号：JP4721582
申请日：1982-03-26
申请人： HITACHI LTD
发明人： MORIWAKI NOBUYUKI , SASAKI KATSUROU , YAMAMOTO AKIRA
IPC分类号： G11C11/417 , G11C11/419
摘要： PURPOSE:To speed up reading operation, by providing an MOST for equalization which turns on at the level of an earth potential side by a one-shot pulse generated before a memory cell is read through a couple of data lines. CONSTITUTION:For an sRAM consisting of an MOS, a P channel MOST-QE1 for equalization is provided between a couple of data lines D and D'. The said gate, a timing pulse phiE from an address input timing detecting circuit is impressed. When address signals ai and ai' vary, the output signal exi of the detecting circuit drops in low level and the timing pulse phiE also drops in low level to turn on the QE1, short-circuiting both data lines D and D'. Thus, both levels are equalized to each other to perform equalization, and reading operation is speeded up.

5. 发明专利

JPS60234292A MOS STATIC RAM 失效
公开(公告)号：JPS60234292A
公开(公告)日：1985-11-20
申请号：JP8941884
申请日：1984-05-07
申请人： HITACHI LTD
发明人： SASAKI KATSUROU , ISHIKAWA SHINJI
IPC分类号： G11C11/417 , G11C11/34
摘要： PURPOSE:To attain the high-speed working of an MOS static RAM by providing a load FET with which a complementary data line is turned on in a non-selection mode. CONSTITUTION:When a complementary data line DO and a line DO', etc. are put under a non-selection state by a low level column selection signal YO, etc., the output YO' of an inverter IVO is changed to a high level. Then load MOSFET Q13 and Q14 connected in parallel to load MOSFETQ5 and Q6 respectively are turned on. Thus the conductances of lines DO and DO' are increased and both lines have an approximately equal potential with no remain of the preceding read information. Therefore, the time is shortened to change the line DO' to a high level according to the storage contents of a memory cell MC. Thus the working speed of an MOS static RAM can be increased.

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