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1. 发明专利

JP2004171742A Semiconductor device 审中-公开
公开(公告)号：JP2004171742A
公开(公告)日：2004-06-17
申请号：JP2003373026
申请日：2003-10-31
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： TAKEMURA RIICHIRO , SEKIGUCHI TOMONORI , SAKATA TAKESHI , MIYATAKE SHINICHI , NODA HIROMASA , KAJITANI KAZUHIKO
IPC分类号： H01L21/8242 , G11C7/00 , G11C11/4076 , G11C11/409 , G11C11/4096 , H01L27/02 , H01L27/108 , H01L31/109
CPC分类号： G11C11/4096 , G11C11/4076 , G11C2207/002 , H01L27/0207 , H01L27/10882 , H01L27/10897
摘要： PROBLEM TO BE SOLVED: To realize both high-speed writing and stable rewriting in the DRAM of a high-speed cycle. SOLUTION: A word line and a Y selection line YS1 are simultaneously activated, write data is written from an IO line IOt/b in a selection data line DL1t/b, and the data of a memory cell is read at an adjacent nonselection amplifier. By dividing the source node of the cross couple CC of a sense amplifier connected to each data line pair for each Y selection line, the driving of the source node by a write selection cross coupling is prevented. The write data is written during reading, a high-speed writing operation is realized, and the driving of the source node by the write sense amplifier is prevented. Thus, at the adjacent sense amplifier, a stable reading operation is realized without being influenced by the write sense amplifier. COPYRIGHT: (C)2004,JPO

2. 发明专利

JPH11316621A CLOCK SYNCHRONIZING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11316621A
公开(公告)日：1999-11-16
申请号：JP34727298
申请日：1998-12-07
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： NODA HIROMASA , NAGASHIMA YASUSHI , IDEI YOJI , AOKI MASAKAZU , TANAKA HITOSHI
IPC分类号： G11C11/407 , G06F1/10 , G11C11/4076 , H03K5/13 , H03L7/00
摘要： PROBLEM TO BE SOLVED: To provide a clock circuit which has high accuracy and high responsiveness by constructing a grid-like delay circuit, successively and inputting input clock signals delayed in a 1st signal transmission direction and acquiring the output signals via the output terminals of plural logical means arrayed in the 1st signal transmission direction at the final stage of a 2nd signal transmission direction. SOLUTION: An output pulse CDMout is supplied to a grid-like delay circuit SQUAD1, and the delayed signal of the circuit SQUAD1 is supplied to an edge detection circuit ED2. The circuit ED2 compares the edge of the delayed signal of each stage of the circuit SQUAD1 with the edge of a clock pulse that is delayed more by a single clock and inputted. When both edges match with each other in terms of time, the final stage of the circuit SQUAD1 is detected. Then a multiplexer MPX3 is controlled by a detection signal CNTLB that is produced by the circuit ED2, and an output pulse EDout is outputted from a grid-like delay circuit SQUAD2.

3. 发明专利

JPH10261288A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10261288A
公开(公告)日：1998-09-29
申请号：JP24269596
申请日：1996-08-26
申请人： HITACHI LTD
发明人： NODA HIROMASA , AOKI MASAKAZU , IDEI YOJI
IPC分类号： G06F1/26 , G06F1/10 , G11C11/407 , G11C11/4076 , H01L27/10 , H03K5/13 , H04L7/00
摘要： PROBLEM TO BE SOLVED: To enhance a synchronization accuracy while expanding a synchrinizable clock frequency band by generating pulses whose duties of input pulse width are made small while providing a pulse generating circuit at the input part of a synchronous mirror delay circuit SMD. SOLUTION: A pulse generating circuit constituted of a delay circuit Pw, an inverter N1 and a NAND gate G1 is provided in this device. The delay time in an input part from an buffer B1 to an inverter N3 is made to be the same d1 as that of a buffer circuit B2 and the delay time of inverter circuits N4, N5 is made to be the same d2 as that of a buffer circuit B3 and also these delay times are set in accordance with the delay time of edges of pulses to be transmitted from a forward delay array FDA to a backward delay array BDA via a mirror control circuit MCC and, moreover, the delay time of output circuit inverters N6, N7 is also made to be d2. At this time, the period from an external clock CLKin till an internal clock CLKout just becomes the double period of that of the CLKin .

4. 发明专利

JPH08306184A DYNAMIC TYPE RAM AND MEMORY MODULE, AND ITS REFRESHING METHOD 失效
公开(公告)号：JPH08306184A
公开(公告)日：1996-11-22
申请号：JP24072995
申请日：1995-08-25
申请人： HITACHI LTD
发明人： IDEI YOJI , SHIMOHIGASHI KATSUHIRO , AOKI MASAKAZU , NODA HIROMASA , SATO KATSUYUKI , IWAI HIDETOSHI , SAEKI AKIRA , MURATA JUN , TADAKI YOSHITAKA , SEKIGUCHI TOSHIHIRO , TSUCHIYA OSAMU
IPC分类号： G11C11/406 , G11C11/407
摘要： PURPOSE: To enable refreshing operation which is suitable for an information holding time and has low power consumption by a carrier signal of a refreshing address counter corresponding to a refreshing period made shorter than the shortest information holding time. CONSTITUTION: An address counter generates refreshing address signals A0-A11, and adds it to a programmable-read-only-memory(PROM). The PROM stores a refreshing address signal corresponding to refreshing time setting information of two values whether a refreshing address signal is a signal of refreshing in a short period or a signal of refreshing in a long period. A carrier signal CARRY from an address counter is frequency-divided to 1/m by a (m) value counter, and generates logical product of refreshing time setting information read out from the PROM with an AND gate circuit. Low power consumption can be attained by refreshing inhibiting signals inhibit-0 to inhibit-3 corresponding respectively to an array block 0-3 to an array block-3.

5. 发明专利

JPH06244415A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06244415A
公开(公告)日：1994-09-02
申请号：JP2773093
申请日：1993-02-17
申请人： HITACHI LTD
发明人： KIMURA SHINICHIRO , KURE TOKUO , NODA HIROMASA
IPC分类号： H01L29/78 , H01L21/336 , H01L29/784
摘要： PURPOSE:To prevent the increase in parastic capacitance and the decrease in carrier mobility to decrease the resistance of a diffused layer by making the gate electrode, formed in a groove, with a gate insulation film in between, contact a diffusion layer, so as to establish contact with the diffused layer by a high conduction layer. CONSTITUTION:With a silicon oxide film 6 and a silicon nitride film 5 as a mask, the exposed part of a semiconductor substrate 1 is etched by RIE for forming a groove, and a gate silicon oxide film 10 is formed inside the groove, and using a CVD method, a conduction film 11 is formed all over it. Arsenic is implanted into the substrate 1 so that a diffused layer is formed. Thus, the depth at the corner of the groove gate 11 agrees with that of the diffused layer 12. Then, after a silicon oxide film is formed all over it, full surface anisotropic etching is done to leave a silicon oxide film 13 on a side wall of the gate electrode 1 as it is, so the surface of the substrate 1 or base material is exposed, and then after arsenic is ion-implanted for forming a high concentration diffused layer 14, thermal treatment is done for a metal film to be deposited all over it, and then, etching is made so that a silicide film 15 is left as it is only on the diffused layers 12 and 14 and the gate electrode 11.

6. 发明专利

JPH0574806A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0574806A
公开(公告)日：1993-03-26
申请号：JP23442691
申请日：1991-09-13
申请人： HITACHI LTD
发明人： KIMURA SHINICHIRO , YADORI SHOJI , NODA HIROMASA , HISAMOTO MASARU , MATSUOKA HIDEYUKI , TORII KAZUNARI , YOKOYAMA NATSUKI , YOSHIMURA TOSHIYUKI , TSUJIMOTO KAZUNORI , TAKEDA EIJI
IPC分类号： H01L29/78 , H01L21/285 , H01L21/336
摘要： PURPOSE:To control impurities at the ends of source-drain by depositing polycrystalline silicon as a diffusion source onto a thin oxide film approximately the same as a natural oxide film, diffusing impurities and removing polycrystalline silicon. CONSTITUTION:A thin oxide film 9 is formed onto the surface of a substrate and the surfaces of sidewall polycrystalline silicon 8. The film thickness is set not to disturb impurity diffusion but to provide the foundation of the machining of polycrystalline silicon. The oxide film 9 is used as the diffusion source of impurity diffusion to the substrate. Polycrystalline silicon 10 is deposited. Impurities are introduced so as to form a desired conductivity type. The polycrystalline silicon film 10 is etched while employing the extremely thin oxide film 9 as a foundation by using an anisotropic dry etching method. Accordingly, diffusion layers at the ends of source-drain can be made shallow while isolating the gate and the source-drain.

7. 发明专利

JP2006351173A SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS 审中-公开
公开(公告)号：JP2006351173A
公开(公告)日：2006-12-28
申请号：JP2006164272
申请日：2006-06-14
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANAKA HITOSHI , AOKI MASAKAZU , KIMURA SHINICHIRO , NODA HIROMASA , SEKIGUCHI TOMONORI
IPC分类号： G11C11/407 , G06F1/26 , G11C11/408 , H01L21/822 , H01L21/8238 , H01L21/8242 , H01L27/04 , H01L27/092 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit apparatus equipped with a stably operated internal power supply circuit or the like. SOLUTION: This apparatus is provided with a power supply circuit operated by a power supply voltage from the outside to form an internal voltage, and an internal circuit to which the internal voltage is applied. A variable impedance means is provided between the output voltage of a charge pump circuit and the internal voltage. A differential amplifying circuit controls the variable impedance means so that a reference voltage corresponding to the internal voltage is compared with the internal voltage and the both are coincident with each other. A power supply circuit is constituted of a first power supply circuit for forming a voltage having a polarity same as that of the voltage supplied from the outside and a second power supply circuit for forming a voltage having a polarity different from the voltage supplied from the out side. The output voltage of the charge pump circuit of the first power supply circuit is applied to an N-well having a P-well forming elements constituting an internal circuit formed therein. The output voltage generated by the charge pump circuit of the second power supply circuit is used also as a substrate back-bias voltage applied to the P-well having the elements constituting the internal circuit formed therein. COPYRIGHT: (C)2007,JPO&INPIT

8. 发明专利

JP2004103657A Semiconductor storage device 有权
公开(公告)号：JP2004103657A
公开(公告)日：2004-04-02
申请号：JP2002260279
申请日：2002-09-05
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KAJITANI KAZUHIKO , NODA HIROMASA , MIYATAKE SHINICHI , TAKEMURA RIICHIRO , SEKIGUCHI TOMONORI , SAKATA TAKESHI
IPC分类号： H01L21/8242 , G11C5/06 , G11C7/18 , G11C11/22 , G11C11/401 , G11C11/4097 , G11C29/50 , H01L27/02 , H01L27/108
CPC分类号： G11C29/50 , G11C7/18 , G11C11/4097 , G11C2207/005 , G11C2211/4013 , H01L27/0207 , H01L27/10882 , H01L27/10897
摘要： PROBLEM TO BE SOLVED: To reduce the contact resistance of each bit line selecting switch and to make the on-resistances of all bit line selecting switches uniform without making an area required for arranging the switches larger.
SOLUTION: The bit line selecting switches 14 are connected to one-side ends of odd-numbered bit lines 12 and to the other-side ends of even-numbered bit lines 12. The odd-numbered and even-numbered bit lines 12 are connected to terminals of sense amplifiers 16 one pair by one pair. Memory cells 13 are arranged at prescribed intersecting points of word lines 11 and bit lines 12 corresponding to a half of all intersecting points of the lines 11 and 12, so that the memory cells 13 connected to one word line 11 are connected electrically to each terminal of a unit circuit 16 one by one when the word line 11 is selected.
COPYRIGHT: (C)2004,JPO

9. 发明专利

JPH11312025A CLOCK GENERATING CIRCUIT 失效
公开(公告)号：JPH11312025A
公开(公告)日：1999-11-09
申请号：JP11768898
申请日：1998-04-28
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： NODA HIROMASA , NAGASHIMA YASUSHI , AOKI MASAKAZU , TANAKA HITOSHI
IPC分类号： G06F1/04 , G06F1/10 , G11C11/407 , H03K3/02 , H03K5/135 , H03L7/00 , H04L7/00
摘要： PROBLEM TO BE SOLVED: To form an inside clock signal of 50% duty factor with a simple configuration, and to highly precisely form an outside synchronizing clock pulse high in responsiveness. SOLUTION: The coincidence of a delay signal in each stage transmitted through a delay circuit DL1 having large time resolution with the clock edge delayed by one clock of an input pulse is detected by an edge detecting circuit ED1, and the delay input clock pulse is transmitted through a delay circuit DL2 so that the same number of delay stages of the delay circuit DL1 can be obtained with the edge detection signal. In the same way, the clock pulse is transmitted through a delay circuit DL3 so that the same number of stages as that of the delay circuit DL2 can be obtained, and the output pulse of the delay circuit DL2 is inputted to a delay circuit DL4, and the coincidence of the delay signal in each stage transmitted through the delay circuit DL4 having small time resolution with the clock edge delayed by two clocks of the input pulse is detected by an edge detecting circuit ED2. Then, an inside clock signal is formed of the delay signal of the delay circuit DL4, and the delay time of a dummy delay circuit is made equal to the synthetic delay time of an input buffer circuit and a clock generating circuit.

10. 发明专利

JPH10144074A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10144074A
公开(公告)日：1998-05-29
申请号：JP31422596
申请日：1996-11-11
申请人： HITACHI LTD
发明人： IDEI YOJI , AOKI MASAKAZU , NODA HIROMASA
IPC分类号： G11C11/407 , G06F1/06 , G06F1/10 , G11C7/10 , H01L27/10 , H03K5/135 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To obtain a synchronous clock generating circuit in which a synchronizable frequency band is expanded by setting a delay time to the delay time made to correspond to the sum between the delay time of an input buffer circuit and the delay time of a clock drive. SOLUTION: The output signal of a clock buffer CKB is transmitted to the start terminal START of the timing generating circuit (TG) constituted of a counter circuit through delay circuits DL1, DL2 in one side and to the reverse terminal REVERSE of the TG in other side. The TG starts a counting operation with a first input signal to be supplied to the start terminal and the counting operation is reversed with a second input signal to be supplied to the reverse terminal and after the time made to correspond to the time difference between the first and second input signals is elapsed, the TG outputs a timing signal. Moreover, the frequency of the oscillation circuit is a frequency sufficiently high with respect to a clock signal CLK and the timing signal formed by the TG forms an internal clock int. CLK via a clock driver CKD.

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