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1. 发明专利

JPH08250682A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH08250682A
公开(公告)日：1996-09-27
申请号：JP6407596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/108
摘要： PURPOSE: To reduce resistance of an interface between a transition metal film buried in a connection hole and an aluminum alloy wiring and hence reduce a disconnection failure of a wiring by providing a barrier layer between the transition metal film and the aluminum alloy wiring. CONSTITUTION: A semiconductor integrated circuit device includes a first wiring 52 formed on a semiconductor substrate 20, and an interlayer insulating film 53 having an opening (connection hole) through which part of the first wiring 52 is exposed and formed on the first wiring 52. It further includes a transition metal film 54 formed over the connection hole 53D in the interlayer insulating film 53 and an aluminum alloy wiring 55B containing an additive Si formed on the transition metal film 54 and the interlayer insulating film 53. Particularly, a barrier layer (transition metal silicide film) 55A is provided between the transition metal film 54 and the aluminum alloy wiring 55B. Hereby, the transition metal silicide film 55A can connect, even if the aluminum alloy wiring 55B is cut down owing to a migration phenomenon for example, the aluminum alloy wirings 55B putting the cut part therebetween, and can hence reduce a disconnection failure of a wiring.

2. 发明专利

JPH08250683A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08250683A
公开(公告)日：1996-09-27
申请号：JP6407796
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L23/522 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/78
摘要： PURPOSE: To improve an adhesion property between a base insulating film and a wiring, and improve processing accuracy of the wiring and a transition metal film underlying the wiring by forming a second metal film formed by a CVD process on a first metal film formed by a sputtering process. CONSTITUTION: This device comprises a plurality of wirings 55 consisting of an insulating film (base insulating film) 53 formed on a principal surface of a semiconductor substrate 20 and a metal film (transition metal film) 54 formed on the base insulating film 53. The transition metal film 54 includes a first metal film formed by a sputtering process and a second metal film formed by a CVD process. The second metal film is formed on the first metal film. The first metal film has its thickness thinner than that of the second metal film. The first and second metal films comprise the same material. Hereby, the transition metal film 54 deposited by a sputtering process has a higher adhesion property with each of the base insulating film 53 and the wiring 55 so that an adhesion property between the base insulating film 53 and the wiring 55 can be improved.

3. 发明专利

JPS5297785A ION SOURCE DEVICE 失效
公开(公告)号：JPS5297785A
公开(公告)日：1977-08-16
申请号：JP1405376
申请日：1976-02-13
申请人： HITACHI LTD
发明人： NIINA TOMOJI
IPC分类号： H01J49/10 , G01N27/62 , H01J49/14 , H01J49/16
摘要： PURPOSE:To simplify the construction of a composite ion source device of field ionization, field dissociation and electron impingement by equipping a specimen holder and an emitter to the same probe.

4. 发明专利

JPH09115838A FILM FORMING SYSTEM 失效
公开(公告)号：JPH09115838A
公开(公告)日：1997-05-02
申请号：JP26977295
申请日：1995-10-18
申请人： HITACHI LTD
发明人： NIINA TOMOJI , OTSUKA MASASHI
IPC分类号： C23C16/44 , C23C16/46 , C23C16/54 , H01L21/205 , H01L21/285 , H01L21/31 , H01L21/68 , H01L21/683
摘要： PROBLEM TO BE SOLVED: To eliminate stand by time in forming thin film with a simple structure and at low cost. SOLUTION: When the film forming of approximately 180 seconds of a wafer W, that is held by a wafer supporting part 3b, is started, another wafer W held by the wafer holding part 3a, of which film forming is just finished, is mounted on an elevator 7, the elevator 7 is lower to a predetermined position and the semiconductor wafer W is cooled for 30 seconds preliminarily. Then the treated semiconductor wafer W is stored and a new semiconductor wafer W, that is before the treatment, is mounted on the elevator 7, the elevator 7 is raised to a position at a predetermined distance from the wafer holding part 3a and the preheating of the wafer W of a approximately 30 seconds is started. By performing the upper stated operation continuously, the treatment of the semiconductor wafers W is proceeded continuously without stand by time.

5. 发明专利

JPS612330A PROCESSING EQUIPMENT 失效
公开(公告)号：JPS612330A
公开(公告)日：1986-01-08
申请号：JP12175284
申请日：1984-06-15
申请人： HITACHI LTD
发明人： KASAHARA OSAMU , NIINA TOMOJI
IPC分类号： H01L21/324 , H01L21/22 , H01L21/31
摘要： PURPOSE:To prevent external atmosphere from entering into a processing chamber by a method wherein a sub-chamber is provided before the processing chamber filled with inert gas atmosphere before the object to be processed is carried in and out of the processing chamber to be in stand-by state. CONSTITUTION:A heat treatment equipment is provided with a process tube 1 while inner chamber is formed of a processing chamber 2 and a heater 3 is provided outside in enclosure. An inlet 4 for supplying inert gas is openly provided on one end of the tube 1 while a furnace door 5 and an outlet 6 are openly provided on one end of the tube 1 while a furnace door 5 and an outlet 6 are openly provided on the other end. A tube 7 forming a spare chamber 8 is continuously connected to the furnace door 5 side while another inlet 9 for inert gas is openly provided on the central part. Besides, a gate valve 10 is interposed between the processing chamber 2 and the spare chamber 8 to be opened and closed freely. The tube 7 is provided with a door 11 for feeding and discharging wafer as well as a shutter 12 made of door bodies 12a, 12b. In such a constitution, a wafer 14 as a work loaded on a loader tube 13 may be held by a jig 15 to be carried in and out of the sub-chamber 8 and the processing chamber 2.

6. 发明专利

JPH09181061A LIQ. MATERIAL GASIFYING METHOD AND FEEDER AND SEMICONDUCTOR PRODUCING APPARATUS CONSTITUTED, USING IT 失效
公开(公告)号：JPH09181061A
公开(公告)日：1997-07-11
申请号：JP33630195
申请日：1995-12-25
申请人： HITACHI LTD
发明人： NIINA TOMOJI , OTSUKA MASASHI
IPC分类号： B05D3/00 , C23C16/44 , C23C16/448 , C23C16/52 , H01L21/205 , H01L21/223 , H01L21/285 , H01L21/31
摘要： PROBLEM TO BE SOLVED: To stably feed a low-concn. dopant gas at high accuracy. SOLUTION: A mass flow controller 5 feeds to a piping 5 a carrier gas at a flow rate enough to control the flow rate at high accuracy, the gas flow rate controlled by the controller 5 is fed into a source tank 6 and an organic boron source is bubbled into a gas, i.e., a high-concn. dopant gas. This gas is mixed with a diluting gas fed at a flow rate controlled by the controller 4 at high accuracy. A controller 9 connected to the piping 8 controls the flow rate optimum for making flat an insulation film formed on the surface of a semiconductor wafer located at a specified position in a reaction chamber HR disposed in a CVD apparatus and feeds the gas through a piping 11 into the chamber HR for doing specified treatment.

7. 发明专利

JPH08241968A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08241968A
公开(公告)日：1996-09-17
申请号：JP6404596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the junction breakdown strength of a substrate to an element and which reduces a leakage current amount at the junction part of the substrate to the element by a method wherein an active region is not arranged in the boundary region between a first channel stopper region and a second channel stopper region. CONSTITUTION: In a DRAM, a memory cell and an n-channel MISFET in a peripheral circuit are arranged respectively on main faces inside respective different active regions in a p-type well region which is prescribed by a p-type channel stopper region formed on the main face of an inactive region in the p-type well region. Here, a p-type channel stopper region 25A which surrounds the circumference of the memory cell and an n-channel stopper region 24 in the peripheral circuit are constituted independently in separate manufacturing processes. Then, an active region Act such as the memory cell, the n-channel MISFET or the like in the peripheral circuit are not arranged in the boundary region between the p-type channel stopper region 25A and the n-type channel region 24.

8. 发明专利

JPS6173334A Treating device 失效
标题翻译：处理设备
公开(公告)号：JPS6173334A
公开(公告)日：1986-04-15
申请号：JP19466484
申请日：1984-09-19
申请人： Hitachi Ltd
发明人： NIINA TOMOJI
IPC分类号： H01L21/205 , H01L21/31
CPC分类号： H01L21/31
摘要： PURPOSE:To improve productivity by disposing a preliminary chamber in the hole of a treating chamber, and standing by an article to be treated before telescoping in the treating chamber in an ambient temperature atmosphere preliminary chamber having no oxygen, thereby avoiding the article to contact with the atmosphere at a high temperature. CONSTITUTION: A hole 7 is formed between a treating chamber 1 and a preliminary chamber 9 of a treating device, reaction gas is supplied from a reaction gas supply passage 2 to the chamber 1, and the chamber 1 is evacuated through an exhaust passage 3. An article 4 to be treated is held in a susceptor 5 in the chamber 1. The first gate valve 8 is provided in the hole 7 between the chambers 1 and 9, and is opened and closed by a handler 15. A hole 12 is formed at the other side wall opposed to the hole 7, the second gate valve of the hole 12 is opened and closed by a handler 16, and the article 4 is held in the cassette 14 of the chamber 1. Inert gas is supplied from an inert gas supply passage 10 to the chamber 1, and stood by in the chamber 9 having no oxygen before telescoping the article 4 in the chamber 1 to prevent it from contacting with the atmosphere at a high temperature.
摘要翻译：目的：为了提高生产率，通过在处理室的孔中设置预备室，并且在没有氧气的环境温度大气预备室中在处理室中伸缩之前待处理物品站立，从而避免物品与在高温下的气氛。构成：在处理装置1的处理室1和预备室9之间形成孔7，将反应气体从反应气体供给路径2供给到室1，通过排气通路3将室1抽真空。要处理的物品4被保持在腔室1中的基座5中。第一闸阀8设置在腔室1和9之间的孔7中，并由处理器15打开和关闭。形成孔12 在与孔7相对的另一侧壁上，孔12的第二闸阀由处理器16打开和关闭，并且物品4保持在室1的盒14中。惰性气体从惰性气体供给通道10到室1，并且在将物品4在室1中伸缩之前站立在没有氧的室9中，以防止其在高温下与大气接触。

9. 发明专利

JPS5843862B2 失效
公开(公告)号：JPS5843862B2
公开(公告)日：1983-09-29
申请号：JP1405376
申请日：1976-02-13
申请人： HITACHI LTD
发明人： NIINA TOMOJI
IPC分类号： H01J49/10 , G01N27/62 , H01J49/14 , H01J49/16

10. 发明专利

JPS52102792A DEPTH CONCENTRATION ANALYZER 失效
公开(公告)号：JPS52102792A
公开(公告)日：1977-08-29
申请号：JP1891376
申请日：1976-02-25
申请人： HITACHI LTD
发明人： NIINA TOMOJI , HATSUTORI TADATETSU
IPC分类号： G01N23/225 , H01J37/252
摘要： PURPOSE:To measure the etching depth by combining a solid analyzer using an ion probe with an electronic microscope of scanning type using an electronic probe having no etching action.

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